Lanny L. Lewyn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A first stage circuit for a pipeline ADC first stage combines the functions of an input sample-and-hold-plus-amplifier (SHA) stage, and the functions of the first analog-to-digital conversion stage of an ADC, including a multiplying DAC (MDAC), stage-flash ADC (SFADC) comparators, and residue opamp (RAMP). The ADC first stage is duplicated, inputs and outputs are connected, and an autozero circuit using a switched-capacitor filter feedback loop controls the RAMP bias circuitry to reduce 1/f noise and DC offsets. The sampling capacitors may be connected to the ADC input for one full sample clock time period and are disconnected from the analog input period before connecting the sampling capacitors to an amplifier voltage output or voltage reference, thereby sampling the input and allowing sufficient time for the SFADC comparators to resolve and control the MDAC capacitor settings with a low metastability error rate.
Abstract: A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially from the second voltage supply. Collector voltage at the output stage is dynamically controlled to be greater than the emitter voltage by a difference voltage that increases proportionally as output voltage increases above the switch-over threshold. This difference voltage is commonly referred to as “headroom.
Abstract: In its broadest terms, the invention is an electrostatically shielded and resistively insulated high-value resistor that is implemented using a CMOS resistive sealing layer of a larger CMOS device. In particular, the IC resistor according to the invention uses a substantially continuous, resistive layer to electrically connect the resistor input and output electrodes, which are formed as portions of a top metal layer. The resistive layer itself forms a resistive electrical path between the input and output, isolation of the resistor from other components on the same integrated circuit being provided without patterning of the resistive layer. An output ring portion of the top metal layer is electrically connected to the output electrode and surrounds the input electrode. A grounded shield ring portion of the top metal layer is also preferably included. The shield ring surrounds the output ring portion and forms a first electrostatic shield for the resistor.
Abstract: A digital-to-analog converter (DAC) includes separate converter segments for converting the most significant bits (MSB's) and next-most-significant bits (NSB's) of a digital input word. The MSB's are converted in a thermometer-encoded capacitive DAC (CDAC), in which the MSB's are decoded and used to control the state of CDAC switches, which connect any of a plurality of CADC reference voltages, through respective unit capacitors, to the DAC output. The NSB's are converted in a preferably binary encoded resistive DAC (RDAC), in which two separate sets (“A” and “B”) of RDAC switches selectively connect a plurality of RDAC reference voltages to respective A and B RDAC output buses. Control circuitry is included to decode and apply the MSB's as state control signals to the CDAC switches on each clock cycle. The NSB's are also decoded and applied as control signals, but on alternate clock cycles, to the A and B RDAC switch sets.
Abstract: A plurality of intermediate driving devices are included in stages between a clock generator and a bank of synchronous logic devices. The outputs of the intermediate devices in each stage are connected in parallel over a wide linear dimension. The timing delay of each circuit is then subject to a small variation depending on the irregularities associated with the device characteristics used in its construction. The outputs of the intermediate devices in each stage are tied together to restore regularity and uniformity to all clock generation circuit outputs.
Abstract: A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially entirely from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially entirely from the second voltage supply. Collector voltage at the output stage can be maintained greater than the emitter voltage by a predetermined, substantially constant amount.
Abstract: The invention provides a stable voltage reference circuit that has a single reference diode junction. Two separate current sources are switched so as to alternately apply a first and second current to the junction, with the second current being larger than the first. The voltage over the junction thereby alternates between a first AC input voltage (V1) that has a positive temperature dependence (dV1/dT) and a second AC input voltage (V2) that has a negative temperature dependence (dV2/dT). Combining circuitry is included for adding the first and second input voltages and for thereby generating an output voltage (Vref) substantially constant with absolute temperature. The combining circuitry preferably includes an amplifier that has, for the first input voltage, a gain substantially equal to the ratio of the negative temperature dependence divided by the positive temperature dependence.
Abstract: A flash converter is preceded by an accurate continuous-time error amplifier operating on the difference between the input signal and a feedback DAC. The DAC output is operatively coupled to the amplifier input virtual ground or summing node through, for example, a set of precision capacitors. The input circuit is also coupled to the amplifier input through a continuous-time element such as a set of precision capacitors, approximately equal in capacitance to those coupled to the DAC. The amplifier may have a moderate closed-loop forward gain such as 16 with a high-pass characteristic beyond, for example, 10 Hz. The DAC is controlled by the latched output of a digital signal processing block, which uses digital outputs from the flash converter and the last latched output to predict the next value of the input signal. Converter control loop stability is afforded by providing a lowpass character to the prediction circuit.
Abstract: The magnitudes of an input voltage and individual ones of progressive fractions of a reference voltage are compared to produce first and second output voltages. Each of the elements in a first logical network receives the first output voltage from an individual one of the comparators and the second output voltage from a comparator non-consecutive with (preferably 2 comparators removed from) such individual comparator. Signals from these elements pass to latches. The latches have assertion and negation outputs which pass to elements in a second logical network. When an individual one of the elements in the second logical network provides a particular output, it prevents the elements receiving outputs from comparators responsive to lower reference voltage fractions from providing the particular output.
Abstract: A circuit for charging a lithium-ion battery and a technique for charging the battery are described. The battery charger takes into account the electrical series resistance (ESR) of the battery. The charger contains a compensation circuit which outputs the battery terminal voltage minus the expected voltage drop across the ESR of the battery. This resulting voltage is then applied to the sense terminals of the power supply. The voltage applied to the sense terminals of the power supply is, thus, representative of the active electrode voltage (AEV) of the battery. The power supply then provides sufficient charging current to maintain the voltage at the sense terminals at a preset voltage limit. Using this technique, the lithium-ion battery is charged to within 99.5% of its full charge in about half of the time required by the prior art.
Abstract: Binary bits of least binary significance are converted to a corresponding analog output. Binary bits of increased binary significance are converted to a first plurality of thermometer outputs. A plurality of switching assemblies, each preferably recursive and preferably formed from a plurality of switches (e.g. transistors), process individual pairs of successive ones of such thermometer outputs. Each stage respectively produces first or second outputs or the analog output for first, second and third relationships between the thermometer outputs in such pair. The analog output has a variable value between the first and second outputs depending upon the value of the least significant binary bits. When the binary value is represented only by the binary bits of least and increased binary significance, the first, second and analog outputs are combined to produce an analog output representative of such binary bits.
Abstract: A first switch (e.g. semiconductor) becomes conductive when at least one of two binary inputs to be added is a binary "1". A second switch (e.g. semiconductor) becomes conductive when there is a carry of a binary "1" from a preceding stage. The semiconductors provide a particular potential on an output line when both semiconductors are conductive. This potential provides a binary carry to a carry switch in the next stage. The carry switch in the next stage is an n-channel semiconductor when the carry switch in the previous stage is a p-channel semiconductor. A logical network also produces a signal when both of the binary inputs are a binary "1". This signal causes a third switch (e.g. semiconductor) to become conductive and to produce the particular voltage on the output line whether or not the particular voltage is produced on the output line by the operation of the first and second switches.
Abstract: A positive energizing voltage, preferably in a CMOS circuit, is converted, primarily by a pair of buffer capacitors and secondarily by a filter capacitor, to a particular negative potential. One buffer capacitor is charged through first switches by the positive voltage during the positive half cycles of a clock signal. The buffer capacitor is discharged to a load during the negative half cycles of the clock signal through a circuit including such buffer capacitor, second switches, a third switch, a reference voltage (e.g. ground) line and a line for providing a negative biasing potential. The other buffer capacitor is charged through fourth switches by the positive voltage during the negative half cycles of the clock signals. This buffer capacitor is discharged to the load during the positive half cycles of the clock signals through a circuit including such other buffer capacitor, fifth switches, the third switch, the reference voltage line and the negative potential line.
Abstract: A balanced cascode current mirror includes first and second current paths respectively defined by first and second transistors and by third and fourth transistors. Each current path may include the sources and drains of the transistors in such path. Connections may respectively extend between the gates of the first and third transistors and between the gates of the second and fourth transistors to provide the first and third transistors with substantially identical source, gate, and drain impedances. An input current is introduced to the drain of the second transistor and an output current with substantially identical characteristics is obtained from the drain of the fourth transistor. A capacitance may be connected between the drain of the second transistor and the gate of the first transistor to produce a flow of current at high frequencies through the first current path corresponding to the input current at the drain of the second transistor.
Abstract: A first film disposed in a first direction on an integrated circuit chip and having uniformly spaced taps provides progressively increasing resistance values. A second film disposed on the chip in a direction opposite to the first direction at a position displaced in any direction from the first film may have a construction corresponding to that of the first film. First and second reference voltages may be respectively applied to the first and second ends of the first and second films. Particular taps on the first film may be connected to taps in corresponding positions on the second film with corresponding voltages. A plurality of differential comparators are provided, each with a signal input and a reference input. Each comparator reference input is connected to an individual one of the taps on the first film, but not necessarily to successive taps. The reference input connections to the taps may have a non-linear (e.g. a luminance) spacing in the first direction to provide a non-linear voltage (e.g.
Abstract: A substantially constant current is divided between two lines in accordance with the relative values of an input voltage and a reference voltage respectively introduced to such lines. The currents through the first and second lines respectively charge first and second capacitances. The charges in the first and second capacitances respectively control the magnitudes of the currents flowing through first and second control members to charge the first and second capacitances. The control members are interconnected so that any difference between the flow of current through the control members and the associated capacitances between magnified. When the charge in an individual one of the capacitances reaches a particular value, a signal on an output terminal associated with the other capacitance changes from the first magnitude to a second magnitude. During this time, the signal associated with the first capacitance remains at substantially the first magnitude.
Abstract: An unknown analog signal is compared in amplitude with the signal from a digital-to-analog (D-A) converter. The converter, preferably monotonic, may be at least partially formed from a plurality of switches connected in a recursive array to define sub-sets having a recurrent relationship. An adjustable-gain amplifier produces a difference signal having an amplitude indicating the amplitude comparison. A flash converter converts the difference signal to binary signals. These binary signals are modified and fed back to the D-A converter to obtain from this converter an output signal having an amplitude approximating the amplitude of the unknown analog signal. A plurality of successive approximations of the analog signal may be provided in this manner. In at least one (1) of these approximations, the gain of the amplifier may be increased to increase the sensitivity of the approximation by increasing the gain of the difference signal.
Abstract: A digital-to-analog converter includes a decoding network and a plurality of output members such as capacitors. The decoding network receives a plurality of binary signals individually having logic levels respectively coding for binary "1" and binary "0" and individually coding for a binary value of an individually weighted significance and cumulatively coding for an analog value. The network decodes the logic levels of the binary signals and activates output members in accordance with such decoding. As the analog value coded by the logic levels of the binary signals increases, the output members previously activated in the plurality remain activated and other output members in the plurality become activated. The decoding network and the output members are disposed on an integrated circuit chip. Dependent upon their positioning on the chip, the output members have different characteristics which cause errors to be produced in the analog signal, particularly at low analog values.
Abstract: A first matrix relationship is defined by a plurality of switches operative in first and second states in accordance with the logic levels of binary signals introduced to the switches. The switches in the matrix relationship receive binary signals of relatively high binary significance. An activating line is connected to the matrix relationship to activate storage members, such as capacitors, connected to the matrix relationship. The number of storage members energized by the activating line at each instant is related to the value coded by the logic levels of the binary signals introduced to the matrix relationship. For increasing binary values, the storage members previously energized in the plurality by the activating line continue to be energized and additional storage members in the plurality are energized. An interpolating line is also provided in the first matrix relationship.
Abstract: We disclose and claim a novel high efficiency oscillator circuit and method of operation wherein output signal distortion is minimized by applying the weighted sum of currents flowing in an input complementary transistor pair to each transistor in an output complementary pair. This operation is accomplished using a novel summing current mirror stage to interconnect the input and output complementary pairs, and the channel width-to-length, W/L, ratios of transistors in the mirror stage sets the value of the weighted sum of currents applied to the complementary pair output stage.