Lanny L. Lewyn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: An operational amplifier circuit including an output stage which requires relatively low operating current to achieve a desired transconductance in order to permit improved driving of a capacitive load.
Abstract: An improved output circuit for an operational amplifier which is controlled to operate in one of two modes. In the first mode, the output of the operational amplifier tracks a reference signal or ground. In the second mode, the output of the operational amplifier tracks the level of a time varying second voltage signal. The improvement consists of replacing the stabilization capacitor of prior art output circuits with a pair of stabilization capacitors connected in parallel. Each of the pair of capacitors has an associated series connected switch for switching the capacitor into and out of the circuit. The switches are operated by a respective one of a pair of external non-overlapping clock pulse trains so as to not be closed simultaneously.
Abstract: In the present invention, channel charge compensation is achieved in a MOS switch comprising two MOSFETs connected in parallel and a compensating MOSFET placed on the semiconductive substrate in precise symmetry with the two switching FETs, each of the FETs being designed to have the same channel charge storing capacity. Accordingly, first order variations in oxide thickness or in gate width across the surface of the semiconductive substrate do not affect the accuracy with which channel charge is compensated in the invention. The compensating FET is switched in complementary fashion with the two switching FETs so that it absorbs one-half of the channel charge expelled from the switching FETs when they are turned off, thus preventing this charge from upsetting other components in the circuit such as precision storage capacitors connected to the switch.
Abstract: The auto-zeroing technique of this invention comprises two steps. In the first step, the differential amplifier output and negative input are shorted together and the resulting amplifier offset output voltage is stored across an input capacitor and a feedback capacitor, the input capacitor being connected between the amplifier negative input and a voltage source to be sampled and the feedback capacitor being connected between the amplifier negative input and ground. In the second step, the direct connection between the amplifier output and negative input is removed and the feedback capacitor is reconnected between the amplifier output and negative input in a feedback loop. At this time, a voltage of the same magnitude and opposite polarity as the original amplifier offset output voltage is applied as negative feedback across the amplifier, so that the amplifier offset output voltage is precisely zeroed. In an alternative embodiment, the connection and reconnection steps are performed at a frequency f.sub.
Abstract: A very low current Pierce oscillator has two pairs of complementary field-effect transistors (FET's) and a two-terminal quartz crystal. The gates of the first complementary FET pair are coupled through individual capacitors to one terminal of the quartz crystal, their drains being connected together and to the other quartz crystal terminal. Current flow through the crystal oscillator is minimized by a novel oscillator bias loop connected between the gates of the first FET pair. Amplification is provided by the second FET pair which have a commonly connected drain comprising the oscillator output node. The gates of the second FET pair are each connected to a respective one of the gates of the first FET pair. The oscillator bias loop minimizes the source-to-drain current through the first FET pair by reducing the P-channel FET gate voltage in response to the source-to-drain current.
Abstract: A pulse IR reflectance plethysmograph system for heart rate measurement and display in a digital watch or as a medical instrument having a novel direct coupled pole zero cancellation circuit that compensates undesirable shaping effects on the heart blood pressure wave. The system utilizes a pulsed LED light emitting diode for transmitting light pulses and a photodiode for receiving light pulses reflecting from a finger.
Abstract: A pulsed IR reflectance plethysmograph for heart rate measurement and display in a digital watch or as a medical instrument using, for example, a pulsed LED light emitting diode for transmitting light pulses and a photodiode for receiving light pulses reflected from a finger. The LED and photodiode are mounted in a small sensor on the watch or medical instrument. The photodiode is connected directly to a signal conditioning circuit which rapidly removes unwanted asynchronous ambient background light signals such as from sunlight, by means of a switched ambient light subtractor circuit which performs the subtraction without requiring amplification or conversion of the detector signal photocurrent to another electrical parameter. The signal current after cancellation of the ambient background signal is sampled in an integrate and hold circuit to provide a heart systolic pressure wave.