Patents by Inventor Larry David Hewitt

Larry David Hewitt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210132675
    Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.
    Type: Application
    Filed: January 15, 2021
    Publication date: May 6, 2021
    Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Yanfeng Wang, Michael J. Tresidder, Kevin M. Lepak, Larry David Hewitt, Noah Beck
  • Patent number: 10895901
    Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 19, 2021
    Assignees: ADVANCED MICRO DEVICES INC., ATI TECHNOLOGIES ULC
    Inventors: Yanfeng Wang, Michael J. Tresidder, Kevin M. Lepak, Larry David Hewitt, Noah Beck
  • Publication number: 20200379544
    Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
  • Patent number: 5964883
    Abstract: An arrangement for monitoring clock frequency variations on a peripheral bus is provided to improve operations of the peripheral device despite changes in the clock frequency. In one aspect of the arrangement, a processing unit is coupled to a host bus which in turn is coupled to a peripheral bus which is coupled to a peripheral device. A monitoring arrangement is provided which detects a change in the clock frequency of the peripheral bus and determines if the frequency change exceeds a threshold associated with the peripheral device. If the threshold is exceeded, the peripheral device is informed that the clock frequency of the peripheral bus has changed. A peripheral device operating a different operating levels may use the information from the monitoring arrangement to alter the operating level of the peripheral device to conform to the new bus clock frequency.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: October 12, 1999
    Assignee: Advanced Micro Devices
    Inventor: Larry David Hewitt