Patents by Inventor Larry Grant Giddens
Larry Grant Giddens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11886360Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.Type: GrantFiled: February 21, 2023Date of Patent: January 30, 2024Assignee: RAMBUS INC.Inventors: Aws Shallal, Larry Grant Giddens
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Publication number: 20230259466Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.Type: ApplicationFiled: February 21, 2023Publication date: August 17, 2023Inventors: Aws Shallal, Larry Grant Giddens
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Patent number: 11615037Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.Type: GrantFiled: May 3, 2021Date of Patent: March 28, 2023Assignee: Rambus Inc.Inventors: Aws Shallal, Larry Grant Giddens
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Patent number: 11443784Abstract: A buffer chip includes a first set of input/output (I/O) pins a second set of I/O pins, and is configurable to operate in one of a first mode or a second mode. The first set of I/O pins and the second set of I/O pins are configured to convey first signals between the buffer chip and one or more volatile memory devices on a memory module when the buffer chip is configured to operate in the first mode. The first set of I/O pins is configured to convey the first signals between the buffer chip and the one or more volatile memory devices and the second set of I/O pins is configured to convey second signals between more non-volatile memory devices on the memory module when the buffer chip is configured to operate in the second mode.Type: GrantFiled: October 7, 2019Date of Patent: September 13, 2022Assignee: Rambus Inc.Inventors: Aws Shallal, Larry Grant Giddens
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Publication number: 20210343318Abstract: A buffer chip includes a first set of input/output (I/O) pins a second set of I/O pins, and is configurable to operate in one of a first mode or a second mode. The first set of I/O pins and the second set of I/O pins are configured to convey first signals between the buffer chip and one or more volatile memory devices on a memory module when the buffer chip is configured to operate in the first mode. The first set of I/O pins is configured to convey the first signals between the buffer chip and the one or more volatile memory devices and the second set of I/O pins is configured to convey second signals between more non-volatile memory devices on the memory module when the buffer chip is configured to operate in the second mode.Type: ApplicationFiled: October 7, 2019Publication date: November 4, 2021Inventors: Aws Shallal, Larry Grant Giddens
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Publication number: 20210311888Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.Type: ApplicationFiled: May 3, 2021Publication date: October 7, 2021Inventors: Aws Shallal, Larry Grant Giddens
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Patent number: 11042492Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.Type: GrantFiled: October 17, 2018Date of Patent: June 22, 2021Assignee: Rambus Inc.Inventors: Aws Shallal, Larry Grant Giddens
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Patent number: 11030118Abstract: In a memory module, encryption information is received from an external source and stored exclusively within a non-persistent storage element such that the encryption information is expunged from the memory module upon power loss. Write data is received and encrypted using the encryption information stored within the non-persistent storage element to produce encrypted data which is stored, in turn, within a nonvolatile storage of the memory module.Type: GrantFiled: December 20, 2017Date of Patent: June 8, 2021Assignee: Rambus Inc.Inventors: Aws Shallal, Larry Grant Giddens, Sarvagya Kochak
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Publication number: 20200226079Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.Type: ApplicationFiled: October 17, 2018Publication date: July 16, 2020Inventors: Aws Shallal, Larry Grant Giddens
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Publication number: 20180260339Abstract: In a memory module, encryption information is received from an external source and stored exclusively within a non-persistent storage element such that the encryption information is expunged from the memory module upon power loss. Write data is received and encrypted using the encryption information stored within the non-persistent storage element to produce encrypted data which is stored, in turn, within a nonvolatile storage of the memory module.Type: ApplicationFiled: December 20, 2017Publication date: September 13, 2018Inventors: Aws Shallal, Larry Grant Giddens, Sarvagya Kochak
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Publication number: 20170200498Abstract: Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Inventors: Aws SHALLAL, Larry Grant GIDDENS
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Patent number: 9639281Abstract: Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller.Type: GrantFiled: September 15, 2016Date of Patent: May 2, 2017Assignee: INPHI CORPORATIONInventors: Aws Shallal, Larry Grant Giddens
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Patent number: 9460791Abstract: Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller.Type: GrantFiled: December 8, 2015Date of Patent: October 4, 2016Assignee: INPHI CORPORATIONInventors: Aws Shallal, Larry Grant Giddens
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Patent number: 6639919Abstract: Methods for bit-level control of dynamic bandwidth allocation are adapted for use in multi-node channelized transport systems. A single status bit is used to indicate the desired allocation status of each transport channel for which dynamic allocation is permitted or desired. The status bit has a first logic level indicative of a desire to have a first allocation status, such as allocated for data traffic, and a second logic level indicative of a desire to have a second allocation status, such as allocated for voice traffic. The status bit may be repeated multiple times within a frame to mitigate the effects of transmission errors. The values of the status bit or bits can be maintained across node boundaries without regard to the framing mechanisms or multiplexing techniques used by the transport system, thus permitting dynamic bandwidth allocation beyond the local loop.Type: GrantFiled: May 1, 2001Date of Patent: October 28, 2003Assignee: ADC DSL Systems, Inc.Inventors: Robert S. Kroninger, Dieter H. Nattkemper, Paul Fitch, Larry Grant Giddens
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Publication number: 20020163936Abstract: Methods for bit-level control of dynamic bandwidth allocation are adapted for use in multi-node channelized transport systems. A single status bit is used to indicate the desired allocation status of each transport channel for which dynamic allocation is permitted or desired. The status bit has a first logic level indicative of a desire to have a first allocation status, such as allocated for data traffic, and a second logic level indicative of a desire to have a second allocation status, such as allocated for voice traffic. The status bit may be repeated multiple times within a frame to mitigate the effects of transmission errors. The values of the status bit or bits can be maintained across node boundaries without regard to the framing mechanisms or multiplexing techniques used by the transport system, thus permitting dynamic bandwidth allocation beyond the local loop.Type: ApplicationFiled: May 1, 2001Publication date: November 7, 2002Applicant: ADC DSL Systems, Inc.Inventors: Robert S. Kroninger, Dieter H. Nattkemper, Paul Fitch, Larry Grant Giddens