Patents by Inventor Larry J. Rasnake

Larry J. Rasnake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8703603
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: April 22, 2014
    Assignee: Nuvotronics, LLC
    Inventors: David W. Sherrer, Larry J. Rasnake, John J. Fisher
  • Publication number: 20110079893
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Application
    Filed: November 11, 2010
    Publication date: April 7, 2011
    Inventors: David W. Sherrer, Larry J. Rasnake, John J. Fisher
  • Patent number: 7888793
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: February 15, 2011
    Assignee: Nuvotronics, LLC
    Inventors: David W. Sherrer, Larry J. Rasnake, John J. Fisher
  • Publication number: 20090154872
    Abstract: Provided are electronic device packages and their methods of formation. The electronic device packages include a sealed volume enclosing an electronic device and a feedthrough into the sealed volume for electrical connection of the electronic device. Provided are optoelectronic device packages and their methods of formation. The optoelectronic device packages include a first substrate and lid attached to the first substrate forming an enclosed volume. An optoelectronic device is disposed within the enclosed volume and a wick stop for preventing solder flow is provided. Provided are prism-coupled optical assemblies which allow for the coupling of light between an optical component, such as a laser, and an integrated optical waveguide through a prism.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 18, 2009
    Inventors: David S. Sherrer, Carl E. Gaebe, James W. Getz, Larry J. Rasnake, William K. Hogan
  • Patent number: 7508065
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: March 24, 2009
    Assignee: Nuvotronics, LLC
    Inventors: David W. Sherrer, Larry J. Rasnake, John J. Fisher
  • Patent number: 7449784
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: November 11, 2008
    Assignee: Nuvotronics, LLC
    Inventors: David W. Sherrer, Larry J. Rasnake, John J. Fisher
  • Patent number: 7329056
    Abstract: Provided are optoelectronic device packages. The packages include a base substrate having an optoelectronic device mounting region on a surface of the base substrate and a lid mounting region. An optoelectronic device is mounted on the optoelectronic device mounting region. A lid is mounted on the lid mounting region to form an enclosed volume between the base substrate and the lid. The optoelectronic device is in the enclosed volume. The lid has an optically transmissive region suitable for transmitting light of a given wavelength along an optical path to or from the optoelectronic device, wherein at least a portion of the lid mounting region is disposed along the optical path below the surface of the base substrate to a depth below the optical path. Also provided are wafer or grid level optoelectronic device packages, wafer- or grid-level optoelectronic device package lid and their methods of formation, and connectorized optoelectronic devices.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: February 12, 2008
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: David W. Sherrer, Larry J. Rasnake, John J. Fisher
  • Patent number: 7198727
    Abstract: The present invention provides an optical microbench having intersecting structures etched into a substrate. In particular, microbenches in accordance with the present invention include structures having a planar surfaces formed along selected crystallographic planes of a single crystal substrate. Two of the structures provided are an etch-stop pit and an anisotropically etched feature disposed adjacent the etch-stop pit. At the point of intersection between the etch-stop pit and the anisotropically etched feature the orientation of the crystallographic planes is maintained. The present invention also provides a method for micromachining a substrate to form an optical microbench. The method comprises the steps of forming an etch-stop pit and forming an anisotropically etched feature adjacent the etch-stop pit. The method may also comprise coating the surfaces of the etch-stop pit with an etch-stop layer.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: April 3, 2007
    Assignee: Shipley Company, L.L.C.
    Inventors: Dan A. Steinberg, Larry J. Rasnake
  • Patent number: 7129163
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: October 31, 2006
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: David W. Sherrer, Larry J. Rasnake, John J. Fisher
  • Patent number: 6907150
    Abstract: The present invention provides an optical microbench having intersecting structures etched into a substrate. In particular, microbenches in accordance with the present invention include structures having a planar surfaces formed along selected crystallographic planes of a single crystal substrate. Two of the structures provided are an etch-stop pit and an anisotropically etched feature disposed adjacent the etch-stop pit. At the point of intersection between the etch-stop pit and the anisotropically etched feature the orientation of the crystallographic planes is maintained. The present invention also provides a method for micromachining a substrate to form an optical microbench. The method comprises the steps of forming an etch-stop pit and forming an anisotropically etched feature adjacent the etch-stop pit. The method may also comprise coating the surfaces of the etch-stop pit with an etch-stop layer.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: June 14, 2005
    Assignee: Shipley Company, L.L.C.
    Inventors: Dan A. Steinberg, Larry J. Rasnake
  • Publication number: 20030067049
    Abstract: The present invention provides an optical microbench having intersecting structures etched into a substrate. In particular, microbenches in accordance with the present invention include structures having a planar surfaces formed along selected crystallographic planes of a single crystal substrate. Two of the structures provided are an etch-stop pit and an anisotropically etched feature disposed adjacent the etch-stop pit. At the point of intersection between the etch-stop pit and the anisotropically etched feature the orientation of the crystallographic planes is maintained. The present invention also provides a method for micromachining a substrate to form an optical microbench. The method comprises the steps of forming an etch-stop pit and forming an anisotropically etched feature adjacent the etch-stop pit. The method may also comprise coating the surfaces of the etch-stop pit with an etch-stop layer.
    Type: Application
    Filed: July 19, 2002
    Publication date: April 10, 2003
    Inventors: Dan A. Steinberg, Larry J. Rasnake