Patents by Inventor Larry James Miller
Larry James Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240086349Abstract: Examples of computing systems that include I/O device(s) that respect an existing hardware resource partitioning in a modern computing platform are provided. The computing systems include at least one CPU having multiple cores and one or more CPU caches. The computing system also includes a main memory having locations, where each location maps to a set in the one or more CPU caches. A first subset of locations is partitioned for thread(s) of a first application and assigned to non-contiguous memory locations of the main memory. The computing system further includes an I/O device separate from the CPU that is configured to store I/O data in a second subset of locations that are different from the first subset of locations. The second subset of locations are non-contiguous memory locations of the main memory that are separated in address space according to a predefined pattern.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Honeywell International Inc.Inventors: Pavel Zaykov, Larry James Miller
-
Patent number: 11847074Abstract: Examples of computing systems that include input/output (I/O) devices that respect an existing hardware resource partitioning in a modern computing platform are provided.Type: GrantFiled: November 2, 2020Date of Patent: December 19, 2023Assignee: Honeywell International Inc.Inventors: Pavel Zaykov, Larry James Miller
-
Publication number: 20230305887Abstract: Embodiments for improved processing efficiency between a processor and at least one coprocessor are disclosed. Some examples are directed to a processor-coprocessor scheduling in which workloads are scheduled to a coprocessor based on a timing window of the processor. In additional or alternative examples, workloads are assigned to the coprocessor based on the processing resources and/or an order of priority. In connection with the disclosed embodiments, the coprocessor can be implemented by a graphics processing unit (GPU), hardware processing accelerator, field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or other processing circuitry. The processor can be implemented by a central processing unit (CPU) or other processing circuitry.Type: ApplicationFiled: March 28, 2022Publication date: September 28, 2023Applicant: Honeywell International s.r.o.Inventors: Pavel Zaykov, Larry James Miller, Humberto Carvalho, Srivatsan Varadarajan
-
Publication number: 20230305888Abstract: Embodiments for improved processing efficiency between a processor and at least one coprocessor are disclosed. Some examples are directed to mapping of workloads to one or more clusters of a coprocessor for execution based on a coprocessor assignment policy. In connection with the disclosed embodiments, the coprocessor can be implemented by a graphics processing unit (GPU), hardware processing accelerator, field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or other processing circuitry. The processor can be implemented by a central processing unit (CPU) or other processing circuitry.Type: ApplicationFiled: March 29, 2022Publication date: September 28, 2023Applicant: Honeywell International s.r.o.Inventors: Pavel Zaykov, Larry James Miller, Humberto Carvalho, Srivatsan Varadarajan
-
Publication number: 20230111174Abstract: Systems and methods for regulating memory utilization for coprocessors are provided. In one embodiment, a computing system comprises: a processor; a compute processor configured to execute one or more kernels; a memory coupled to the processor and the compute processor. The system is configured to: allocate at least one task memory transaction quota to at least a first set of tasks executed on a first core of the processor; allocate at least one compute processor memory transaction quota for executing the kernels on the compute processor; execute within a first timing window iteration the first set of tasks and the kernels, wherein the kernels are executed during the first timing window iteration until the compute memory transaction quota is depleted; and regulate a rate of memory transaction access by the one or more kernels to the memory when the first set of tasks are executing on the processor.Type: ApplicationFiled: October 13, 2021Publication date: April 13, 2023Applicant: Honeywell International s.r.o.Inventors: Pavel Zaykov, Humberto Carvalho, Larry James Miller
-
Patent number: 11579959Abstract: In one embodiment, a method for margin determination for a computing system with a real time operating system and priority preemptive scheduling comprises: scheduling a set of tasks to be executed in one or more partitions, wherein each is assigned a priority, wherein the tasks comprise periodic and/or aperiodic tasks; executing the set of tasks on the computing system within the scheduled periodic time window; introducing an overhead task executed for an execution duration controlled either by the real time operating system or by the overhead task; controlling the overhead task to converge on a point of failure at which a length of the execution duration of the overhead task causes either: 1) a periodic task to fail to execute within a deadline, or 2) time available for the aperiodic tasks to execute to fall below a threshold; and defining a partition margin corresponding to the point of failure.Type: GrantFiled: May 26, 2021Date of Patent: February 14, 2023Assignee: Honeywell International Inc.Inventors: Larry James Miller, Pavel Zaykov
-
Publication number: 20220382610Abstract: In one embodiment, a method for margin determination for a computing system with a real time operating system and priority preemptive scheduling comprises: scheduling a set of tasks to be executed in one or more partitions, wherein each is assigned a priority, wherein the tasks comprise periodic and/or aperiodic tasks; executing the set of tasks on the computing system within the scheduled periodic time window; introducing an overhead task executed for an execution duration controlled either by the real time operating system or by the overhead task; controlling the overhead task to converge on a point of failure at which a length of the execution duration of the overhead task causes either: 1) a periodic task to fail to execute within a deadline, or 2) time available for the aperiodic tasks to execute to fall below a threshold; and defining a partition margin corresponding to the point of failure.Type: ApplicationFiled: May 26, 2021Publication date: December 1, 2022Applicant: Honeywell International Inc.Inventors: Larry James Miller, Pavel Zaykov
-
Patent number: 11507420Abstract: Systems and methods for scheduling tasks using sliding time windows are provided. In certain embodiments, a system for scheduling the execution of tasks includes at least one processing unit configured to execute multiple tasks, wherein each task in the multiple tasks is scheduled to execute within a scheduler instance in multiple scheduler instances, each scheduler instance in the multiple scheduler instances being associated with a set of time windows in multiple time windows and with a set of processing units in the at least one processing unit in each time window, time windows in the plurality of time windows having a start time and an allotted duration and the scheduler instance associated with the time windows begins executing associated tasks no earlier than the start time and executes for no longer than the allotted duration, and wherein the start time is slidable to earlier moments in time.Type: GrantFiled: September 8, 2020Date of Patent: November 22, 2022Assignee: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Arthur Kirk McCready, Aaron R. Larson, Richard Frost, Ryan Lawrence Roffelsen
-
Patent number: 11409643Abstract: Techniques for determining worst-case execution time for at least one application under test are disclosed using memory thrashing. Memory thrashing simulates shared resource interference. Memory that is thrashed includes mapped memory, and optionally shared cache memory.Type: GrantFiled: February 19, 2020Date of Patent: August 9, 2022Assignee: Honeywell International IncInventors: Pavel Zaykov, Larry James Miller, Srivatsan Varadarajan
-
Publication number: 20220138131Abstract: Examples of computing systems that include input/output (I/O) devices that respect an existing hardware resource partitioning in a modern computing platform are provided.Type: ApplicationFiled: November 2, 2020Publication date: May 5, 2022Applicant: Honeywell International Inc.Inventors: Pavel Zaykov, Larry James Miller
-
Patent number: 11138043Abstract: Systems and methods for outlier mitigation in safety-critical systems are provided. In one embodiment, a computer system comprises: a processor comprising one or more processing cores; a scheduling function that schedules the execution of applications, the applications each comprise threads; a contingency budgeting manager (CBM) that defines at least a first pre-determined set of threads from the threads of the applications and assigns a contingency budget pool to the first set of threads. The first set of threads are each scheduled by the scheduling function to execute on a first processing core. The CBM is further configured to monitor execution of each of the threads of the first set of threads to identify when a first thread is an execution time outlier. When the CBM determines that the first thread is an execution time outlier, it allocates additional thread execution time from the contingency budget pool to the first thread.Type: GrantFiled: May 23, 2019Date of Patent: October 5, 2021Assignee: Honeywell International s.r.oInventors: Pavel Zaykov, Larry James Miller, Srivatsan Varadarajan, Chittaranjan Kashiwar
-
Publication number: 20210133088Abstract: Techniques for determining worst-case execution time for at least one application under test are disclosed using memory thrashing. Memory thrashing simulates shared resource interference. Memory that is thrashed includes mapped memory, and optionally shared cache memory.Type: ApplicationFiled: February 19, 2020Publication date: May 6, 2021Applicant: Honeywell International Inc.Inventors: Pavel Zaykov, Larry James Miller, Srivatsan Varadarajan
-
Patent number: 10908955Abstract: A method is provided. The method comprises: commencing a time window, where the time window has a fixed or variable time duration; determining a shared resource access quota for at least one time partition for the time window, where the shared resource access quota may vary by time window; allocating each determined shared resource access quota to a corresponding time partition for the window; determining if allocated shared resource access quota for any time partition in the time window has been met or exceeded; and if an allocated shared resource access quota for a time partition in the time window has been met or exceeded, then halting an executing process in the time partition.Type: GrantFiled: March 22, 2018Date of Patent: February 2, 2021Assignee: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Chittaranjan Kashiwar, Pavel Zaykov
-
Publication number: 20200401450Abstract: Systems and methods for scheduling tasks using sliding time windows are provided. In certain embodiments, a system for scheduling the execution of tasks includes at least one processing unit configured to execute multiple tasks, wherein each task in the multiple tasks is scheduled to execute within a scheduler instance in multiple scheduler instances, each scheduler instance in the multiple scheduler instances being associated with a set of time windows in multiple time windows and with a set of processing units in the at least one processing unit in each time window, time windows in the plurality of time windows having a start time and an allotted duration and the scheduler instance associated with the time windows begins executing associated tasks no earlier than the start time and executes for no longer than the allotted duration, and wherein the start time is slidable to earlier moments in time.Type: ApplicationFiled: September 8, 2020Publication date: December 24, 2020Applicant: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Arthur Kirk McCready, Aaron R. Larson, Richard Frost, Ryan Lawrence Roffelsen
-
Publication number: 20200371840Abstract: Systems and methods for outlier mitigation in safety-critical systems are provided. In one embodiment, a computer system comprises: a processor comprising one or more processing cores; a scheduling function that schedules the execution of applications, the applications each comprise threads; a contingency budgeting manager (CBM) that defines at least a first pre-determined set of threads from the threads of the applications and assigns a contingency budget pool to the first set of threads. The first set of threads are each scheduled by the scheduling function to execute on a first processing core. The CBM is further configured to monitor execution of each of the threads of the first set of threads to identify when a first thread is an execution time outlier. When the CBM determines that the first thread is an execution time outlier, it allocates additional thread execution time from the contingency budget pool to the first thread.Type: ApplicationFiled: May 23, 2019Publication date: November 26, 2020Applicant: Honeywell International s.r.o.Inventors: Pavel Zaykov, Larry James Miller, Srivatsan Varadarajan, Chittaranjan Kashiwar
-
Patent number: 10768984Abstract: Systems and methods for scheduling tasks using sliding time windows are provided. In certain embodiments, a system for scheduling the execution of tasks includes at least one processing unit configured to execute multiple tasks, wherein each task in the multiple tasks is scheduled to execute within a scheduler instance in multiple scheduler instances, each scheduler instance in the multiple scheduler instances being associated with a set of time windows in multiple time windows and with a set of processing units in the at least one processing unit in each time window, time windows in the plurality of time windows having a start time and an allotted duration and the scheduler instance associated with the time windows begins executing associated tasks no earlier than the start time and executes for no longer than the allotted duration, and wherein the start time is slidable to earlier moments in time.Type: GrantFiled: June 11, 2015Date of Patent: September 8, 2020Assignee: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Arthur Kirk McCready, Aaron R. Larson, Richard Frost, Ryan Lawrence Roffelsen
-
Publication number: 20190294472Abstract: A method is provided. The method comprises: commencing a time window, where the time window has a fixed or variable time duration; determining a shared resource access quota for at least one time partition for the time window, where the shared resource access quota may vary by time window; allocating each determined shared resource access quota to a corresponding time partition for the window; determining if allocated shared resource access quota for any time partition in the time window has been met or exceeded; and if an allocated shared resource access quota for a time partition in the time window has been met or exceeded, then halting an executing process in the time partition.Type: ApplicationFiled: March 22, 2018Publication date: September 26, 2019Applicant: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Chittaranjan Kashiwar, Pavel Zaykov
-
Publication number: 20160364267Abstract: Systems and methods for scheduling tasks using sliding time windows are provided. In certain embodiments, a system for scheduling the execution of tasks includes at least one processing unit configured to execute multiple tasks, wherein each task in the multiple tasks is scheduled to execute within a scheduler instance in multiple scheduler instances, each scheduler instance in the multiple scheduler instances being associated with a set of time windows in multiple time windows and with a set of processing units in the at least one processing unit in each time window, time windows in the plurality of time windows having a start time and an allotted duration and the scheduler instance associated with the time windows begins executing associated tasks no earlier than the start time and executes for no longer than the allotted duration, and wherein the start time is slidable to earlier moments in time.Type: ApplicationFiled: June 11, 2015Publication date: December 15, 2016Inventors: Srivatsan Varadarajan, Larry James Miller, Arthur Kirk McCready, Aaron R. Larson, Richard Frost, Ryan Lawrence Roffelsen
-
Patent number: 9465664Abstract: Systems and methods for allocation of environmentally regulated slack are provided. In one embodiment, a time-partitioned processing system comprises: at least one processing core; a memory coupled to the processing core; a real-time operating system including a scheduler configured to partition processing time for the processing core into a plurality of time periods, wherein the scheduler further budgets a pre-determined duration of processing time for executing a first budgeted time partitioned entity (TPE) by allocating at least a first allocation of time to the first budgeted TPE; wherein the scheduler utilizes at least a portion of processing time not used to execute the first budgeted TPE or any other budgeted TPE as environmentally regulated slack; wherein the scheduler allocates at least a portion of environmentally regulated slack to one or more slack consuming TPEs based on a measurement of one or more operational environment parameters associated with the processing core.Type: GrantFiled: September 9, 2015Date of Patent: October 11, 2016Assignee: Honeywell International Inc.Inventor: Larry James Miller
-
Patent number: 9207977Abstract: Embodiments of the present invention provide improved systems and methods for grouping instruction entities. In one embodiment, a system comprises a processing cluster to execute software, the processing cluster comprising a plurality of processing units, wherein the processing cluster is configured to execute the software as a plurality of instruction entities. The processing cluster is further configured to execute the plurality of instruction entities in a plurality of execution groups, each execution group comprising one or more instruction entities, wherein the processing cluster executes a group of instruction entities in the one or more instruction entities in an execution group concurrently. Further, the execution groups are configured so that a plurality of schedule-before relationships are established, each schedule-before relationship being established among a respective set of instruction entities by executing the plurality of instruction entities in the plurality of execution groups.Type: GrantFiled: February 6, 2012Date of Patent: December 8, 2015Assignee: Honeywell International Inc.Inventors: Arvind Easwaran, Larry James Miller