Abstract: A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI device. In accordance with the present invention, a modified 5N march test sequence is performed on the embedded RAM devices. The modified 5N March test sequence is a simple algorithm implemented in programmable hardware that has the capability of ensuring that the embedded RAM devices are functional and that they meet the recovery time requirements. The preferred mode of the present invention uses this algorithm to determine if the embedded RAMs are operating properly before the VLSI devices are used in card assembly. However, this method can also be used after card assembly to monitor the embedded RAM's integrity.

Abstract: A random access memory system having at least four independent access ports. In the preferred mode, a random access memory core is accessible by two independent read ports and two independent write ports. The four ports can separately and simultaneously access the same or different addressable locations within the random access memory core, except for collision conditions. A collision condition occurs whenever more than one write ports attempt to simultaneously write into the same addressable location. Such a simultaneous write access to the same cell could produce a metastable condition wherein the data storage state is indeterminate. Collision conditions result in the aborting of at least one of the write accesses on a priority basis. The abort function also protects the hardware from short circuit.

Abstract: A bus control and error detection system is provided for a bus system in which data and address signals are transferred between a microsequencer and a number of operational stations which are coupled to the bus. Tri-state drivers are employed in the microsequencer and in the stations which are constructed such that two of the three states of these tri-state drivers are utilized to provide the two states of binary logic operation, and the third state is a high impedance state that protects the components that are coupled to the bus during predefined abort condition which are detected in the system. An abort detection circuit is included in each of the operational stations which is coupled to receive control signals from the microsequencer and which is constructed to emit an ABORT signal output to the microsequencer when the control signals indicate that an abort condition has occurred for the associated operational station.

Abstract: A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop.

Abstract: An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.

Abstract: A multiple phase clock distribution system for allowing a circuit load to be clocked on predetermined phases of a single clock signal is provided. A single phase clock is the triggering signal for each circuit load in the system, and enable signals are provided to each circuit load to allow the single phase clock to be recognized at only upon an active logic level of the chosen enable signal at a particular circuit load. The enable signals are of duration equal to one period of the single phase clock, and are activated nearly one period of the single phase clock before the triggering edge of the clock to provide as long of an enable signal stabilization period as possible before the single phase clock transitions to its active logic level. Enable signal combination circuitry exists to combine individual enable signals so that varying-frequency enable signals can be produced, and can therefore emulate a multiple phase clock regardless of the number of phases desired.

Abstract: A system for apportioning serially supplied data among eight contending memory banks tends to equalize usage among the banks despite their arrangement in a predetermined, sequential priority. Each bank has a data hold register, an OR logic gate to generate a request signal whenever its register contains data, and a negative AND gate for enabling the bank for clearing data from its register. All except the lowest priority bank further include a blocking latch and an enabling NOR gate. Each blocking latch is set when its associated bank is enabled, and then inhibits its associated AND gate and each higher priority AND gate, while enabling each lower priority NOR gate. Each enabled NOR gate provides an enabling signal to all lower priority AND gates. When the lowest priority AND gate is enabled by the NOR gates and its request signal, all blocking latches are cleared. The banks thus are utilized in a sequence that is maintained even if one or more banks are bypassed on occasion.

Abstract: A multi-processing system of the type having a plurality of MSUs is provided with a support controller in each MSU. Each of the MSUs is provided with a plurality of the interface registers, one for each associated MSU to be connected to the master MSU. Each support controller in each MSU is provided with an initial program load (IPL) controller and each IPL controller is provided with a scan settable control coupled to an external keyboard or console which permits unique scan settable information to be loaded into the IPL controller for setting the interface registers and for interconnecting the MSUs in a desired multi-processing configuration.

Abstract: An improved system for interconnecting main storage units is provided wherein each main storage unit is provided with a support control card and each support control card is provided with interface connection means comprising X-1 number of interfaces where X is a value equal to the number of MSUs. And means for enabling the connection of the interfaces between different pairs of MSUs to operably connect any number of said X number of MSUs to a plurality of data processors employing X(X-1)/2 pairs of cables.

Abstract: A novel memory access system is provided for simultaneously processing request for access to a plurality of memory banks. A plurality of input-output ports are coupled to a read bus and to a write bus which are in turn coupled to the memory banks to be accessed by read and write commands initiated by processors coupled to the I/O ports. Pipeline control means receive the request for access functions from the processors and are operable to resolve conflict between plural request. The pipeline control means sequentially raise either write or read request on control and address buses and generate time slot windows during which subsequent write or read data transfer operations will occur so that data being pipelined on the write and read buses is being simultaneously accessed.

Abstract: A system for apportioning serially supplied data among eight contending memory banks tends to equalize usage among the banks despite their arrangement in a predetermined, sequential priority. Each bank has a data hold register, an OR logic gate to generate a request signal whenever its register contains data, and a negative AND gate for enabling the bank for clearing data from its register. All except the lowest priority bank further include a blocking latch and an enabling NOR gate. Each blocking latch is set when its associated bank is enabled, and then inhibits its associated AND gate and each higher priority AND gate, while enabling each lower priority NOR gate. Each enabled NOR gate provides an enabling signal to all lower priority AND gates. When the lowest priority AND gate is enabled by the NOR gates and its request signal, all blocking latches are cleared. The banks thus are utilized in a sequence that is maintained even if one or more banks are bypassed on occasion.

Abstract: Apparatus for detecting and isolating the occurrence of faults in a digital electronic system so as to reduce the mean-time-to-repair. Associated with the logic circuitry to be monitored is a fault indicator which produces a fault signal when a malfunction occurs. Fault capture circuitry is arranged in a hierarchical manner and provides a group fault output signal when one of the fault indicators generates a fault signal. A programmable controller is provided which receives the group fault signal as an interrupt and which then responds by transferring registered fault event signals to a dynamic string register, rearming the error detection used to trap a fault signal and logging the fault location in a memory for later readout by a maintenance processor or the like. The dynamic string allows communications to take place using a scan/set protocol.

Abstract: A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each provided with a fault indicating circuit in series therewith. Each of said fault indicating circuits have logic gating means which include a bit register for each of the bits of a data byte and a parity bit. The output of the bit register means are coupled to isolation drivers which in turn are connected to parity checking circuits and the buses for indicating errors which occur in the bytes of a data word without degrading or delaying data transmission to and from said read and write buses.

Abstract: A novel unconditional clock and automatic refresh logic system is provided which comprises a source of unconditional clock pulses coupled to the memory control logic in a manner which permits automatic refreshing of a dynamic memory. There is further provided clock logic means which sense the conditions in the dynamic memory system during which the dynamic memory is not being refreshed. There is further provided, means for generating automatic clock refresh signals coupled to the memory control logic for initiating continuous automatic refresh cycles when the system clock is being shutdown.

Abstract: Logic checking circuits are provided for verifying whether or not the data bus enable logic circuits are operating properly in response to operational commands to transmit or to NOT transmit data. The transmit latches in the bus interface logic circuits are continuously monitored to determine if they are set or NOT set in a position to enable transmission of data or NOT to enable transmission of data to a bus. Transmit gating circuit means are couple to the output of said transmit latches for determining if all of the transmit latches are in the same state and are in the state ordered by the central controller, and for determining whether the state ordered by the central controller occurs in the exact time period during which the command to transmit should be executed.

Abstract: The logic cards for a main storage unit or computer logic which receive request operations for access to portions of the memory or logic are divided into banks or elements. When a request operation attempts to access one of the elements a return busy signal is raised from that element. The present invention structure generates a predicted busy signal which occurs during the same time the return busy signal should be activated or operable. The return busy signal and predict busy signal are compared in novel circuitry to verify that the element performing the operaton is in fact performing an operation during the predetermined time slot allowed for performance of the requested operation. Fault signals for bank invalidation are stored in internal check trap circuitry for future reference when the requestor raises a subsequent request operation.

Abstract: A dynamic random access memory (DRAM) memory refreshing scheme utilizes at least two separate refresh channels. Each of the channels consists of a pair of identical counters which are coupled through two different types of timing chains. One of the timing chains is associated with one of the counters and generates a refresh request signal, while the other timing channel generates a refresh error signal. As long as the refresh error signal matches the refresh request signal, no error is present, and a validated refresh request signal will be generated from that timing channel and supplied to an OR gate to refresh all of the memory banks for the memory.

Abstract: A dual priority hold register enables the transfer of data to memory ports having serial priority in accordance with two stages of priority. First, all latches of a high priority sector of the register are cleared. Then, the highest priority latch of the low priority sector of the register is cleared, while the latches of the higher priority register are loaded with further data. Following clearance of the low priority latch, all latches of the higher priority register are cleared once again, followed by clearance of the next highest priority latch of the lower priority register sector while the higher priority register is loaded once again. The sequence is repeated until both the higher and lower priority sectors of the register are clear.

Abstract: An improved Scientific Processor for use in a data processing system having a general purpose host processor and a High Performance Storage Unit, and under operational control of the host processor is described. The Scientific Processor includes a Vector Processor Module and a Scalar Processor Module, each operable at comparable rates, wherein scalar operands and vector operands can be manipulated in various combinations under program control of an associated host processor, all without requirement of dedicated storage or caching. The Scalar Processor Module includes instruction flow control circuitry, loop control circuitry for controlling nested loops, and addressing circuitry for generating addresses to be referenced in the High Performance Storage Unit. A scalar processor arithmetic logic unit is described for performing scalar manipulations. The Vector Processor Module includes vector control circuitry and vector file storage circuitry together with vector file loading and vector storage circuitry.

Abstract: An instruction flow control system includes an instruction buffer for receiving stored program instructions. A program address generator signals the instruction buffer for fetching the instructions. A translate RAM decodes the fetched instructions and a translate map gate array generates an address to the translate RAM in response to mapped and remapped instructions being fetched from the instruction buffer. The map gate array looks at an operation code included in the instructions and determines if remapping is required. If so, an address is generated including a constant providing a block of specific addresses and a variable providing a specific address within the block. The mapped instruction includes a seven bit operation code field and, in response to a mapped instruction being fetched, all of the seven bits are mapped directly to the translate RAM address.