Patents by Inventor Laung-Terng Wang

Laung-Terng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9696377
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: July 4, 2017
    Assignee: SYNTEST TECHNOLOGIES, INC.
    Inventors: Laung-Terng Wang, Hsin-Po Wang, Xiaoqing Wen, Meng-Chyi Lin, Shyh-Horng Lin, Ta-Chia Yeh, Sen-Wei Tsai, Khader S. Abdel-Hafez
  • Patent number: 9678156
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: June 13, 2017
    Assignee: SYNTEST TECHNOLOGIES, INC.
    Inventors: Laung-Terng Wang, Po-Ching Hsu, Xiaoqing Wen
  • Publication number: 20160131707
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Application
    Filed: January 19, 2016
    Publication date: May 12, 2016
    Inventors: Laung-Terng Wang, Po-Ching Hsu, Xiaoqing Wen
  • Patent number: 9316688
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 19, 2016
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Po-Ching Hsu, Xiaoqing Wen
  • Patent number: 9274168
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: March 1, 2016
    Assignee: SYNTEST TECHNOLOGIES, INC.
    Inventors: Laung-Terng Wang, Po-Ching Hsu, Xiaoqing Wen
  • Publication number: 20150338465
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Application
    Filed: July 21, 2015
    Publication date: November 26, 2015
    Inventors: Laung-Terng WANG, Po-Ching HSU, Xiaoqing WEN
  • Publication number: 20150338461
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Application
    Filed: July 29, 2015
    Publication date: November 26, 2015
    Applicant: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Hsin-Po Wang
  • Publication number: 20150316616
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Application
    Filed: June 22, 2015
    Publication date: November 5, 2015
    Inventors: LAUNG-TERNG WANG, PO-CHING HSU, XIAOQING WEN
  • Patent number: 9121902
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 1, 2015
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Hsin-Po Wang
  • Patent number: 9110139
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: August 18, 2015
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Hsin-Po Wang
  • Patent number: 9091730
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: July 28, 2015
    Assignee: SYNTEST TECHNOLOGIES, INC.
    Inventors: Laung-Terng Wang, Po-Ching Hsu, Xiaoqing Wen
  • Patent number: 9057763
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: June 16, 2015
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
  • Patent number: 9046572
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: June 2, 2015
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Po-Ching Hsu, Xiaqing Wen
  • Patent number: 9026875
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
  • Patent number: 8949299
    Abstract: A method and apparatus for generating a pseudorandom sequence using a hybrid ring generator with low hardware cost. When a primitive polynomial over GF(2) is selected as the characteristic polynomial f(x) to construct a hybrid ring generator, the circuit implementing f(x) will generate a maximum-length sequence (m-sequence). The hybrid ring generator offers unmatched benefits over existing linear feedback shift register (LFSR) based maximum-length sequence generators (MLSGs). Assume k 2-input XOR gates are required in a standard or modular LFSR design. These benefits include requiring only (k+1)/2 2-input XOR gates, having at most one level of a 2-input XOR gate between any pair of flip-flops, enabling the output of each flip-flop to drive at most 2 fanout nodes, and creating a highly regular structure that makes the new design more layout and timing friendly.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: February 3, 2015
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Nur A. Touba
  • Publication number: 20140344636
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Applicant: SYNTEST TECHNOLOGIES, INC.
    Inventors: Laung-Terng Wang, Hsin-Po Wang
  • Publication number: 20140223251
    Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
    Type: Application
    Filed: November 27, 2013
    Publication date: August 7, 2014
    Applicant: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Po-Ching Hsu, Xiaqing Wen
  • Patent number: 8775985
    Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 8, 2014
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Xiaoqing Wen
  • Publication number: 20140149816
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 29, 2014
    Applicant: SYNTEST TECHNOLOGIES, INC.
    Inventors: Laung-Terng Wang, Hsin-Po Wang
  • Publication number: 20140143623
    Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicant: Syntest Technologies, Inc.
    Inventors: Nur A. TOUBA, Laung-Terng WANG, Shianling WU