Abstract: A very fast BCD-to-binary converter useful for addressing a digital memory. The converter includes a logical level comprised of at least three specially chosen AND-OR-INVERT integrated circuit gates, having at least five inputs, for producing binary output signals representing bits of the converted binary number.

Abstract: A BCD-to-binary converter employing a plurality of levels of logical circuitry which provides for the addition of BCD bits based on a powers of 2 expansion of each BCD digit. At least one level of logic circuitry comprises a PROM arrangement in which each PROM is of sufficient size to prevent a carry from being generated therefrom taking into account that a BCD digit cannot exceed a value of 9. Also, at least one PROM is provided with the capability of adding a greater number of BCD bits than the maximum PROM inputs available by proper choice of the particular BCD inputs applied thereto and the particular manner in which the PROM is programmed.

Abstract: A digital data transmission system wherein pairs of binary input signals are encoded into a three-level signal. The encoding is chosen so as to permit selectively choosing for at least one input pair a pair of transmitted levels having either a positive or negative average value relative to a desired intermediate value. Encoding is then chosen so as to continually seek maintenance of the desired intermediate value for the transmitted three-level signal.

Abstract: A serial digital data transmission system wherein pairs of binary input signals are encoded into a self-clocked three-level signal having high, low and intermediate levels for driving over a transmission line with level transitions occurring in response to an applied clock signal, and with a valid signal being employed to indicate data presence. Selectable encoding is provided in response to detecting any accumulated excess of high or low prior transmission levels so as to continually seek maintenance of an intermediate average level for the transmitted signal. The clock and valid signals are regenerated at the receiver for use in deriving the binary signal data from the received three-level signal.

Abstract: A PROM binary adder useful in a BCD-to-binary converter which provides for the addition of BCD bits based on a powers of 2 expansion of each BCD digit. The PROM binary adder comprises a PROM arrangement in which at least one PROM is provided with the capability of adding a greater number of input bits than the maximum PROM inputs available by proper choice of the particular inputs applied thereto and the particular manner in which the PROM is programmed.

Abstract: A two-wire digital data transmission system wherein pairs of binary input signals are encoded into a self-clocked three-level signal. Predetermined start bits and a valid signal are employed in a manner which permits signal reversing to automatically occur at the receiving end so as to provide proper polarity for the received signal.

Abstract: A network apparatus whereby a high frequency transmission line may be switched and distributed to any one of a selected number of outputs without disturbing the characteristic impedance or continuity of the transmission line. Transmission strip lines on a printed circuit board connect each of the two outputs of a single pole double-throw reed relay to the single input of a subsequent double-throw relay. The relay switches and the transmission strip lines are parallel to an embedded ground plane within the printed circuit board. Each realy switch is surrounded by an electromagnetic shield which is connected at both its input end and its output end to the ground plane in the most direct fashion. Actuating means are provided proximate to each relay switch for activation purposes.