Abstract: An EDA tool is provided with the ability to determine a cell based parallel verification order for a plurality of hierarchically organized design cells of an integrated circuit design, and the ability to verify the design cells in accordance with the cell based parallel verification order, with at least some of the design cells being verified in parallel. In one embodiment, the EDA tool is also provided with the ability to re-express a design cell of the IC design in terms of a number of newly formed intervening constituent design cells, with the new intervening constituent design cells being formed in accordance with a number of metrics profiling placements of original constituent design cells of the design cell.

Abstract: An EDA tool is provided with the ability to re-express a design cell of an IC design in terms of placements of a number of newly formed intervening constituent design cells, the IC design having a number of hierarchically organized placements of design cells. The new intervening constituent design cells is formed in accordance with a number of metrics profiling placements of the original constituent design cells of the design cell. The EDA tool is also provided with the ability to determine the metrics. In one embodiment, the metrics are weights reflective of at least edge placement activities associated with row/column coordinates of the design cell. Th EDA tool determines these weights associated with the row/column coordinates, and then uses the determined weights to select a subset of the row/column coordinates as cut line coordinates to logically partition the design cell into a number of regions.

Abstract: An EDA tool is provided with the ability to determine a cell based parallel verification order for a plurality of hierarchically organized design cells of an integrated circuit design, and the ability to verify the design cells in accordance with the cell based parallel verification order, with at least some of the design cells being verified in parallel . In one embodiment, the EDA tool is also provided with th ability to re-express a design cell of the IC design in terms of a number of newly formed intervening constituent design cells, with the new intervening constituent design cells being formed in accordance with a number of metrics profiling placements of original constituent design cells of the design cell.

Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

Abstract: A calculator is defined by a user-interface centered around a last in first out stack of mathematical or logical objects, that is both visible and accessible to a user. Objects may be any of a number of different types, each type characterized by specific logical or mathematical rules. Calculator operations are provided that may be applied in a uniform manner to the objects, affecting either or both the internal composition of the objects or the external positions and number of the objects on the stack. Objects of different types are distinguished upon entry on the stack and in visible display by characteristic prefix and postfix symbols, and can be entered from a keyboard or created dynamically as the result of calculator operations.

Abstract: A method and apparatus for recovery of a computation stack in a calculator is presented in accordance with a preferred embodiment of the present invention. In a calculator employing a stack for the storage of data to be utilized in a calculation, provision is made to store the contents of the stack before a calculation is performed. If, after the calculation is performed a user desires to "undo" the calculation, he may strike an "undo" key. The original state of the stack is then restored.