Patents by Inventor Laurent F. Stadler

Laurent F. Stadler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7702840
    Abstract: Lane configuration of an interface device of an integrated circuit is described. A core is used to tile a portion of an integrated circuit with a first version of the core and a second version of the core. The core is an application specific circuit version of an interface device. The first version and the second version in combination have a sharable interface. Each of the first version and the second version has N lanes. The first version is a primary version and the second version is a secondary version responsive to a shared interface mode. The N lanes of the second version are combined with the N lanes of the first version via the sharable interface for providing 2-by-N lanes of input/output to the first version.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: April 20, 2010
    Assignee: XILINX, Inc.
    Inventors: Patrick C. McCarthy, Laurent F. Stadler
  • Patent number: 7626418
    Abstract: A configurable interface for an integrated circuit is described. The integrated circuit includes a first core, where the first core is an application specific circuit version of a Peripheral Component Interconnect Express (“PCIe”) interface device. First configuration memory cells are associated with the first core, and the first configuration memory cells are for configuring the first core. The first configuration memory cells are programmable responsive to a first portion of a configuration bitstream, and the configuration bitstream is capable of including user-logic information for programming programmable logic of the integrated circuit.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: December 1, 2009
    Assignee: Xilinx, Inc.
    Inventors: Paige A. Kolze, Laurent F. Stadler, Patrick C. McCarthy
  • Patent number: 7573295
    Abstract: A hard macro-to-user logic interface of an integrated circuit is described. The integrated circuit includes a core as an application specific circuit block with a transaction interface of a first bit width and includes programmable logic capable of being programmed to instantiate user logic. The user logic has a user interface of a second bit width substantially less than the first bit width. A wrapper circuit couples the user interface and the transaction interface for coupling the core to the user logic.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: August 11, 2009
    Assignee: XILINX, Inc.
    Inventor: Laurent F. Stadler