Patents by Inventor Laurent-Georges Gosset

Laurent-Georges Gosset has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130286540
    Abstract: A method of forming a metal- insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 31, 2013
    Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Patent number: 8470685
    Abstract: The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing (42) an intertrack dielectric deposited on an interconnect structure surface to control the height between the top surface of a metal line of the interconnect surface and the surface of the intertrack dielectric; depositing (44) a dielectric liner on the interconnect surface; removing (46) at least part of the dielectric liner on the interconnect surface; successively repeating (48) the deposition of the dielectric liner and the removal of the dielectric liner on the interconnect surface in so far as the interconnect surface is sufficiently protected by a remaining dielectric liner for forming of the plurality of air cavity trenches; and forming (50) at least one air cavity trench in-between the metal lines by etching the intertrack dielectric material.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: June 25, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Patent number: 8424177
    Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 23, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)
    Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Patent number: 8138082
    Abstract: A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: March 20, 2012
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninkljike Philips Electronics N.V.
    Inventors: Joaquin Torres, Vincent Arnal, Laurent-Georges Gosset, Wim Besling
  • Patent number: 8110879
    Abstract: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: February 7, 2012
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Publication number: 20110080686
    Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
    Type: Application
    Filed: May 6, 2010
    Publication date: April 7, 2011
    Applicants: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)
    Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Publication number: 20100090346
    Abstract: The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing (42) an intertrack dielectric deposited on an interconnect structure surface to control the height between the top surface of a metal line of the interconnect surface and the surface of the intertrack dielectric; depositing (44) a dielectric liner on the interconnect surface; removing (46) at least part of the dielectric liner on the interconnect surface; successively repeating (48) the deposition of the dielectric liner and the removal of the dielectric liner on the interconnect surface in so far as the interconnect surface is sufficiently protected by a remaining dielectric liner for forming of the plurality of air cavity trenches; and forming (50) at least one air cavity trench in-between the metal lines by etching the intertrack dielectric material.
    Type: Application
    Filed: January 11, 2007
    Publication date: April 15, 2010
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Publication number: 20100059889
    Abstract: The present invention relates to a method for fabricating a semiconductor device. For improving the adhesion between a copper-containing interconnect element and a diffusion barrier on top of it, a first dielectric layer (108) of a first dielectric material is deposited on an exposed surface (102.1) of the interconnect element. Susequently, particles (110) are implanted into the first dielectric layer and the interconnect element (102) so as to let the interconnect material mix with the first dielectric material in a first interface region (102.2) between the interconnect element and the first dielectric layer.
    Type: Application
    Filed: December 7, 2007
    Publication date: March 11, 2010
    Applicant: NXP, B.V.
    Inventors: Laurent Georges Gosset, Joaquin Torres, Sonarith Chhun
  • Publication number: 20100038797
    Abstract: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.
    Type: Application
    Filed: October 19, 2009
    Publication date: February 18, 2010
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Patent number: 7630191
    Abstract: A capacitor formed in an insulating porous material.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: December 8, 2009
    Assignee: STMicroelectronics Crolles 2 SAS
    Inventors: Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Patent number: 7605071
    Abstract: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: October 20, 2009
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Publication number: 20090218699
    Abstract: A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.
    Type: Application
    Filed: February 26, 2007
    Publication date: September 3, 2009
    Inventors: Joaquin Torres, Vincent Arnal, Laurent-Georges Gosset, Wim Besling
  • Patent number: 7553739
    Abstract: An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper interconnects. A polymer material is introduced on the edges of interconnect lines and vias within an interconnect stack. This incorporates and controls air cavities formation, thus enhancing the signal propagation performance of the semiconductor interconnects.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: June 30, 2009
    Assignees: STMicroelectronics (Corlles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Publication number: 20070200197
    Abstract: A capacitor formed in an insulating porous material.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 30, 2007
    Applicant: STMicroelectronics Crolles 2 SAS
    Inventors: Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Publication number: 20070054485
    Abstract: An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper interconnects. A polymer material is introduced on the edges of interconnect lines and vias within an interconnect stack. This incorporates and controls air cavities formation, thus enhancing the signal propagation performance of the semiconductor interconnects.
    Type: Application
    Filed: July 11, 2006
    Publication date: March 8, 2007
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Joaquin TORRES, Laurent-Georges Gosset
  • Publication number: 20070037380
    Abstract: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.
    Type: Application
    Filed: July 7, 2006
    Publication date: February 15, 2007
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset