Abstract: A system for testing a set of integrated circuits (ICs) that may be implemented as dies in a group of wafers or as packaged ICs mounted in a group of load boards includes a test head for testing the ICs and a prober or handler for holding each wafer or load board with the IC in electrical contact with the test head so that it may be tested. The test system employs a host computer to coordinate activities of the test head and the prober or handler. Software executed by the host computer is partitioned into a device interface function library (DIFL) for communicating with the prober or handler and test head control program for communicating with the test head and for indirectly communicating with the prober or handler by making function calls to the DIFL.