Patents by Inventor Lawrence A. Clevenger

Lawrence A. Clevenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnects having spacers for improved top via critical dimension and overlay tolerance
    Patent number: 11295978
    Abstract: A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert Robison
  • Top vias with selectively retained etch stops
    Patent number: 11289371
    Abstract: Integrated chips and methods of forming the same include forming conductive lines on an underlying layer, between regions of dielectric material. The regions of dielectric material are selectively patterned, leaving at least one dielectric remnant region. An interlayer dielectric is formed over the underlying layer and the at least one dielectric remnant region, between the conductive lines.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: March 29, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert Robison
  • Projected phase change memory devices
    Patent number: 11283015
    Abstract: A method of forming a phase change memory device is provided. The method includes forming a spacer layer on a substrate, and forming a heater terminal contact in the spacer layer. The method further includes forming a liner layer on the heater terminal contact and the spacer layer, and forming a heater terminal in electrical contact with the heater terminal contact in the liner layer. The method further includes forming a conductive projection segment on the heater terminal. The method further includes forming a phase change material layer on the conductive projection segment, and forming a phase change material terminal on the phase change material layer, wherein an electrical current can pass between the heater terminal and the phase change material terminal through the phase change material layer.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 22, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Mathew Philip, Nicole Saulnier, Lawrence A. Clevenger
  • Adjustable via dimension and chamfer angle
    Patent number: 11276636
    Abstract: Chamfer-less via interconnects and techniques for fabrication thereof with a protective dielectric arch are provided. In one aspect, a method of forming an interconnect includes: forming metal lines in a first dielectric; depositing an etch stop liner onto the first dielectric; depositing a second dielectric on the etch stop liner; patterning vias and a trench in the second dielectric, wherein the vias are present over at least one of the metal lines, and wherein the patterning forms patterned portions of the second dielectric/etch stop liner over at least another one of the metal lines; forming a protective dielectric arch over the at least another one of the metal lines; and filling the vias/trench with a metal(s) to form the interconnect which, due to the protective dielectric arch, is in a non-contact position with the at least another one of the metal lines. An interconnect structure is also provided.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Koichi Motoyama, Gangadhara Raja Muthinti, Cornelius Brown Peethala, Benjamin D. Briggs, Michael Rizzolo
  • Conductive lines with subtractive cuts
    Patent number: 11276639
    Abstract: Integrated chips and methods of forming lines in the same include forming a line layer on a substrate. An opening is etched into the line layer that exposes the substrate. A plug is formed in the opening. The line layer is patterned to form a line that terminates at the plug.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: March 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert Robison
  • Top via on subtractively etched conductive line
    Patent number: 11276611
    Abstract: A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Brent Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert Robison
  • Proximity correction in three-dimensional manufacturing
    Patent number: 11263068
    Abstract: Methods and systems for printing accurate three-dimensional structures include printing an original three-dimensional structure according to an original three-dimensional model. The original three-dimensional model is adjusted to reduce measured differences between the printed three-dimensional structure and the original three-dimensional model, by adding material to the original three-dimensional model in proportion to an amount of thermal contraction in a region. An adjusted three-dimensional structure is printed according to the adjusted three-dimensional model.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis G. Sipolins
  • Interconnects having a via-to-line spacer for preventing short circuit events between a conductive via and an adjacent line
    Patent number: 11244859
    Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for forming interconnects using a conductive spacer configured to prevent a short between a via and an adjacent line. In a non-limiting embodiment of the invention, a first conductive line and a second conductive line are formed in a metallization layer. A conductive spacer is formed on the first conductive line and a conductive via is formed on a surface of the conductive spacer. The conductive via is positioned such that the conductive spacer is between the first conductive line and the conductive via. A height of the conductive spacer is selected to provide a predetermined distance from the conductive via to the second conductive line. The predetermined distance from the conductive via to the second conductive line is sufficient to prevent a short between the conductive via and the second conductive line.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Koichi Motoyama, Cornelius Brown Peethala, Christopher J. Penny, Nicholas Anthony Lanzillo, Lawrence A. Clevenger
  • INTERNET OF THINGS (IOT) REAL-TIME RESPONSE TO DEFINED SYMPTOMS
    Publication number: 20220032000
    Abstract: Systems, computer-implemented methods and/or computer program products that facilitate real-time response to defined symptoms are provided. In one embodiment, a computer-implemented method comprises: monitoring, by a system operatively coupled to a processor, a state of an entity; detecting, by the system, defined symptoms of the entity by analyzing the state of the entity; and transmitting, by the system, a signal that causes audio response or a haptic response to be provided to the entity, wherein transmission of the signal that causes the audio response or the haptic response is based on detection of the defined symptoms.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 3, 2022
    Inventors: Mahmoud Amin, Krishna R. Tunga, Lawrence A. Clevenger, Zhenxing Bi, Leigh Anne H. Clevenger
  • Subtractive Line with Damascene Second Line Type
    Publication number: 20220037205
    Abstract: Interconnect structures having subtractive line with damascene second line type are provided. In one aspect, an interconnect structure includes: first metal lines of a first line type disposed on a substrate; and at least one second metal line of a second line type disposed on the substrate between two of the first metal lines, wherein the first line type includes subtractive lines and the second line type includes damascene lines such that the first metal lines have a different metallization structure from the at least one second metal line. A method of forming an interconnect structure is also provided.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 3, 2022
    Inventors: Brent Anderson, Christopher J. Penny, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert ROBISON
  • TOP VIA STACK
    Publication number: 20220028783
    Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer. The semiconductor structure further includes a first conductive material disposed on a top surface of the first conductive line in the first via. The semiconductor structure further includes a second conductive material disposed on a top surface of the second conductive line in the second via.
    Type: Application
    Filed: October 7, 2021
    Publication date: January 27, 2022
    Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
  • TOP VIA INTERCONNECT HAVING A LINE WITH A REDUCED BOTTOM DIMENSION
    Publication number: 20220028785
    Abstract: A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.
    Type: Application
    Filed: October 7, 2021
    Publication date: January 27, 2022
    Inventors: Brent Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert ROBISON
  • Stepped top via for via resistance reduction
    Patent number: 11232977
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: January 25, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
  • Fully Aligned Via for Interconnect
    Publication number: 20220020688
    Abstract: A fully aligned via interconnect structure and techniques for formation thereof using subtractive metal patterning are provided. In one aspect, an interconnect structure includes: metal lines Mx?1; metal lines Mx disposed over the metal lines Mx?1; and at least one via Vx?1 fully aligned between the metal lines Mx?1 and the metal lines Mx, wherein a top surface of at least one of the metal lines Mx?1 has a stepped profile. In another aspect, another interconnect structure includes: metal lines Mx?1; metal lines Mx disposed over the metal lines Mx?1; at least one via Vx?1 fully aligned between the metal lines Mx?1 and the metal lines Mx; and sidewall spacers alongside the metal lines Mx. A method of forming an interconnect structure is also provided.
    Type: Application
    Filed: July 18, 2020
    Publication date: January 20, 2022
    Inventors: Ruilong Xie, Christopher J. Waskiewicz, Chih-Chao Yang, Lawrence A. Clevenger, Ashim DUTTA
  • Enhancement of iso-via reliability
    Patent number: 11227796
    Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 18, 2022
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Lawrence A. Clevenger, Baozhen Li, Xiao H. Liu, Kirk D. Peterson
  • Self-aligned pattern formation for a semiconductor device
    Patent number: 11227793
    Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Nicole Saulnier
  • Trapezoidal Interconnect at Tight BEOL Pitch
    Publication number: 20220013406
    Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Inventors: Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang, Junli Wang, Koichi Motoyama, Christoher J. Penny, Lawrence A. Clevenger
  • TOP VIA WITH DAMASCENE LINE AND VIA
    Publication number: 20220005732
    Abstract: A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.
    Type: Application
    Filed: September 20, 2021
    Publication date: January 6, 2022
    Inventors: Lawrence A. Clevenger, Brent Anderson, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert Robison
  • ETCH STOP LAYER REMOVAL FOR CAPACITANCE REDUCTION IN DAMASCENE TOP VIA INTEGRATION
    Publication number: 20220005731
    Abstract: A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.
    Type: Application
    Filed: September 20, 2021
    Publication date: January 6, 2022
    Inventors: Christopher J. Penny, Brent Anderson, Lawrence A. Clevenger, Robert Robison, Kisik Choi, Nicholas Anthony Lanzillo
  • TOP VIA WITH NEXT LEVEL LINE SELECTIVE GROWTH
    Publication number: 20220005761
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.
    Type: Application
    Filed: September 15, 2021
    Publication date: January 6, 2022
    Inventors: Brent Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert ROBISON