Abstract: This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of the wafer. During the optical testing, the vertical spacing between an optical probe and the wafer is set to a very close distance, to achieve efficient optical coupling. It is beneficial to keep this close distance during optical testing as a constant in testing different optical components at different locations on the wafer. In one implementation, a spacing sensor may be used to measure the height of the optical probe from the wafer surface. This sensor may be a capacitance sensor that is mounted at the optical probe.

Abstract: An optical wavelength grating coupler incorporating one or more distributed Bragg reflectors (DBR) or other reflective elements to enhance the coupling efficiency thereof. The grating coupler has a grating comprising a plurality of scattering elements adapted to scatter light along a portion of an optical path, and the one or more DBRs are positioned with respect to the grating such that light passing through the grating towards the substrate of the grating coupler is reflected back by DBRs toward the grating. The DBR comprises a multilayer stack of various materials and may be formed on the substrate of the grating coupler. The grating coupler may include a gas-filled cavity, where the cavity is formed by a conventional etching process and is used to reflect light toward the grating. The grating coupler may also incorporate an anti-reflection coating to reduce reflective loss on the surface of the grating.

Abstract: An optical wavelength grating coupler incorporating one or more distributed Bragg reflectors (DBR) or other reflective elements to enhance the coupling efficiency thereof. The grating coupler has a grating comprising a plurality of scattering elements adapted to scatter light along a portion of an optical path, and the one or more DBRs are positioned with respect to the grating such that light passing through the grating towards the substrate of the grating coupler is reflected back by DBRs toward the grating. The DBR comprises a multilayer stack of various materials and may be formed on the substrate of the grating coupler. The grating coupler may include a gas-filled cavity, where the cavity is formed by a conventional etching process and is used to reflect light toward the grating. The grating coupler may also incorporate an anti-reflection coating to reduce reflective loss on the surface of the grating.

Abstract: A fiber to chip coupling connecting an optical fiber to an integrated circuit. A section of fiber is laid on top of the surface of the chip, where the end of the fiber has been cut at an angle to form an angled tip. The angled tip has a flat surface which reflects light down to a waveguide grating coupler disposed on the integrated circuit. Light is reflected off the reflective surface of the angled tip by total internal reflection. The waveguide grating coupler is designed to accept the slightly diverging light beam from the reflective surface of the angled tip of the fiber. Light can also propagate through the fiber to chip coupler in the opposite direction, up from the substrate through the waveguide grating and into an optical fiber after bouncing off the reflective surface of the angled tip.

Abstract: Electronically controllable arrayed waveguide gratings (AWGs) with integrated phase error compensation for each individual arm of the array of waveguides. These AWGs and associated methods for static and dynamic phase compensation enable the fabrication of tunable AWGs which can track one or more drifting channels of an AWG.

Abstract: A standard CMOS process is used to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. A polysilicon strip loaded waveguide is used as an example to illustrate the invention. The waveguide has a two layer core made of a polysilicon strip on a silicon slab. In a standard CMOS process, a layer of metallic salicide is deposited for metallic contacts for electronic components, such as transistors. In the present invention, prior to the deposition of the salicide, a salicide blocking layer is selectively deposited for protecting silicon waveguide against damages. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.

Abstract: High speed optical modulators can be made of a lateral PN diode formed in a strip loaded optical waveguide on a SOI or other silicon based substrate. A PN junction is formed at the boundary of the P and N doped regions. The depletion region at the PN junction overlaps with the center of a guided optical mode propagating through the waveguide. Electrically modulating a lateral PN diode causes a phase shift in an optical wave propagating through the waveguide. Due to differences in fabrication methods, forming strip loaded waveguides with consistent properties for use in PN diode optical modulators is much easier than fabricating similar rib waveguides.

Abstract: A standard CMOS process is modified to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. A polysilicon strip loaded waveguide is used as an example to illustrate the invention. The waveguide has a three layer core made of a polysilicon strip on a silicon slab with a silicon dioxide layer between the strip and the slab. In a standard CMOS process, a layer of metallic salicide is deposited for metallic contacts for electronic components, such as transistors. In the present invention, prior to the deposition of the salicide, a salicide blocking layer is selectively deposited for protecting silicon waveguide against damages. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.

Abstract: High speed optical modulators can be made of a reverse biased lateral PN diode formed in a silicon rib optical waveguide disposed on a SOI or other silicon based substrate. A PN junction is formed at the boundary of the P and N doped regions. The depletion region at the PN junction overlaps with the center of a guided optical mode propagating through the waveguide. Electrically modulating a reverse biased lateral PN diode causes a phase shift in an optical wave propagating through the waveguide. Prior art forward biased PN and PIN diode modulators have been relatively low speed devices.

Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical devices such as the core of an optical waveguide or a light scatterer will damage the devices and prevent the passage of light through those sections of the devices. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

Abstract: High speed optical modulators can be made of a lateral PN diode formed in a silicon optical waveguide, disposed on a SOI or other silicon based substrate. A PN junction is formed at the boundary of the P and N doped regions. The depletion region at the PN junction overlaps with the center of a guided optical mode propagating through the waveguide. Electrically modulating a lateral PN diode causes a phase shift in an optical wave propagating through the waveguide. Each of the doped regions can have a stepped or gradient doping profile within it or several doped sections with different doping concentrations. Forming the doped regions of a PN diode modulator with stepped or gradient doping profiles can optimize the trade off between the series resistance of the PN diode and the optical loss in the center of the waveguide due to the presence of dopants.

Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

Abstract: A polarization splitting grating coupler (PSGC) connects an optical signal from an optical element, such as a fiber, to an optoelectronic integrated circuit. The PSGC separates a received optical signal into two orthogonal polarizations and directs the two polarizations to separate waveguides on an integrated circuit. Each of the two separated polarizations can then be processed, as needed for a particular application, by the integrated circuit. A PSGC can also operate in the reverse direction, and couple two optical signals from an integrated circuit to two respective orthogonal polarizations of one optical output signal sent off chip to an optical fiber.

Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.