Abstract: Processing circuitry includes key store hardware that stores a plurality of encryption keys. Key stream generator hardware generates a plurality of key streams from the plurality of encryption keys, wherein each key stream comprises a repeating stream of key data. Key river generator hardware generates a key river by parallelizing the plurality of key streams as key river symbols, wherein bits from each key river symbol are selected from each key stream as individual bits from differing ones of the plurality of encryption keys. Binary processor hardware generates a key path as a sequence of binary digits generated from at least one binary function of the key river.

Abstract: Processing circuitry includes key store hardware that stores a plurality of encryption keys. Key stream generator hardware generates a plurality of key streams from the plurality of encryption keys, wherein each key stream comprises a repeating stream of key data. Key river generator hardware generates a key river by parallelizing the plurality of key streams as key river symbols, wherein bits from each key river symbol are selected from each key stream as individual bits from differing ones of the plurality of encryption keys. Binary processor hardware generates a key path as a sequence of binary digits generated from at least one binary function of the key river.

Abstract: A system includes a key path generator that generates a key path based on a plurality of encryption keys. A block coding unit generates a plurality of codewords based on a plurality of data blocks. A block scrambling unit scrambles the plurality of codewords to generate a plurality of encrypted blocks by entropy processing, chaos processing and permutation processing each of the plurality of codewords, based on the plurality of encryption keys.

Abstract: A system includes a key path generator that generates a key path based on a plurality of encryption keys. A block coding unit generates a plurality of codewords based on a plurality of data blocks. A block scrambling unit scrambles the plurality of codewords to generate a plurality of encrypted blocks by entropy processing, chaos processing and permutation processing each of the plurality of codewords, based on the plurality of encryption keys.

Abstract: A system includes a key path generator that generates a key path based on a plurality of encryption keys. A block coding unit generates a plurality of codewords based on a plurality of data blocks. A block scrambling unit scrambles the plurality of codewords to generate a plurality of encrypted blocks by entropy processing, chaos processing and permutation processing each of the plurality of codewords, based on the plurality of encryption keys.

Abstract: A system includes a key path generator that generates a key path based on a plurality of encryption keys. A block descrambling unit generates a plurality of codewords to by de-entropy processing, de-chaos processing and de-permutation processing each of a plurality of encrypted blocks. A decoder generates a plurality of data blocks by decoding the plurality of codewords.

Abstract: A system includes a key path generator that generates a key path based on a plurality of encryption keys. A block descrambling unit generates a plurality of codewords to by de-entropy processing, de-chaos processing and de-permutation processing each of a plurality of encrypted blocks. A decoder generates a plurality of data blocks by decoding the plurality of codewords.

Abstract: A system includes a key path generator that generates a key path based on a plurality of encryption keys. A block coding unit generates a plurality of codewords based on a plurality of data blocks. A block scrambling unit scrambles the plurality of codewords to generate a plurality of encrypted blocks by entropy processing, chaos processing and permutation processing each of the plurality of codewords, based on the plurality of encryption keys.

Abstract: A method and data processing system are disclosed for storing data in a cache memory and retrieving data from a cache memory in a selected one of multiple data formats. According to the present invention, bits are selected from an L-byte data word to produce N input words, which each have m bits. The N input words are then stored within the cache memory. In response to receipt of a request for data within the L-byte data word having a selected one of the multiple data formats, the N input words are recalled from the cache memory and simultaneously formatted to produce a P-byte formatted data word. Thus, a P-byte formatted data word is efficiently retrieved from the cache memory and formatted according to a selected one of multiple data formats before being utilized in the data processing system.