Patents by Inventor Lawrence T. Clark

Lawrence T. Clark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9117746
    Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: August 25, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Samuel Leshner
  • Patent number: 9112495
    Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 18, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, David A. Kidd, Augustine Kuo
  • Patent number: 9112484
    Abstract: An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 18, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, David A. Kidd, Chao-Wu Chen
  • Patent number: 9070477
    Abstract: A method can include applying a device power supply voltage to an integrated circuit including a static random access memory (SRAM) with transistors having at least a first threshold voltage (Vt); applying an array power supply voltage to cells of the SRAM that is near or below Vt; and in a write operation, reading data from at least a first group of the cells that is interleaved with a second group of the cells, and applying the read data to the bit lines of the first group of cells, while write data is applied to the bit lines of the second group of cells.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: June 30, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventor: Lawrence T. Clark
  • Patent number: 9054688
    Abstract: This disclosure relates generally to sequential state elements (SSEs). More specifically, embodiments of flip-flops are disclosed, along with computerized methods and systems of designing the same. In one embodiment, the flip-flop includes a substrate and subcircuits that are formed on the substrate. The subcircuits provide subfunctions, wherein each of the subcircuits provides at least one of the subfunctions. More specifically, the subfunctions are provided in a sequential logical order by the subcircuits so that the flip-flop provides a flip-flop function. However, the subcircuits are interleaved out of the sequential logical order with respect to a corresponding subfunction provided by each of the subcircuits along a vector defined by the substrate. In this manner, interleaving the subcircuits along the vector of the substrate can provide separation between charge collection nodes without requiring increases in size. Thus, the flip-flop can be more compact and less expensive to manufacture.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: June 9, 2015
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Sandeep Shambhulingaiah, Sushil Kumar, Chandarasekaran Ramamurthy
  • Patent number: 9041429
    Abstract: The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: May 26, 2015
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Arizona State University
    Inventor: Lawrence T. Clark
  • Patent number: 9038012
    Abstract: The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: May 19, 2015
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Nathan D. Hindman, Dan Wheeler Patterson
  • Patent number: 8995204
    Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: March 31, 2015
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Bruce McWilliams, Robert Rogenmoser
  • Patent number: 8966329
    Abstract: In general, each parallel test operation on Static Random Access Memory (SRAM) cells is a test operation performed on a block of the SRAM cells in parallel, or simultaneously. In one embodiment, the SRAM cells are arranged into multiple rows and multiple columns where the columns are further arranged into one or more column groups. The block of the SRAM cells for each parallel test operation includes SRAM cells in two or more of the rows, SRAM cells in two or more columns in the same column group, or both SRAM cells in two or more rows and SRAM cells in two or more columns in the same column group.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: February 24, 2015
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Yu Cao
  • Publication number: 20150015334
    Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
    Type: Application
    Filed: September 29, 2014
    Publication date: January 15, 2015
    Inventors: Lawrence T. Clark, Scott E. Thompson
  • Publication number: 20140331197
    Abstract: The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
    Type: Application
    Filed: June 13, 2014
    Publication date: November 6, 2014
    Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Lawrence T. Clark, Nathan D. Hindman, Dan Wheeler Patterson
  • Patent number: 8860197
    Abstract: An integrated circuit device that is secure from invasion and related methods are disclosed herein. Other embodiments are also disclosed herein.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: October 14, 2014
    Assignee: Arizona Board of Regents, a Body Corporate of the State of Arizona Acting for and on Behalf of Arizona State University
    Inventors: Lawrence T. Clark, David R. Allee
  • Patent number: 8860575
    Abstract: Embodiments of flexible identification systems are described herein. Other embodiments and related methods are also disclosed herein.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 14, 2014
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, Acting for and on behalf of Arizona, State University
    Inventors: David R. Allee, Lawrence T. Clark, Terry L. Alford, Constantine A. Balanis, James T. Aberle, Kevin Baugh
  • Patent number: 8863064
    Abstract: A method for modifying a design of an integrated circuit includes obtaining design layout data for the integrated circuit and selecting at least one SRAM cell in the integrated circuit to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer. The method also includes extracting, from the design layout, NMOS active area patterns and PMOS active area patterns associated with the SRAM cell to define an EBE NMOS active area layout and a EBE PMOS active area layout. The method further includes adjusting the EBE NMOS active area layout to reduce a width of at least pull-down devices in the SRAM cell and altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 14, 2014
    Assignee: SuVolta, Inc.
    Inventors: George Tien, David A. Kidd, Lawrence T. Clark
  • Patent number: 8847684
    Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: September 30, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lawrence T. Clark, Scott E. Thompson
  • Patent number: 8837230
    Abstract: A memory circuit device having at least one test element interconnecting memory sections can include at least one first switch coupled to a first memory section between a first node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and a second node; wherein the forced voltage node is selectively coupled to receive a forced voltage substantially the same as a voltage applied to the second node, and the second node is coupled to at least a second memory section.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: September 16, 2014
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Richard S. Roy
  • Patent number: 8816754
    Abstract: An integrated circuit can include an operational section comprising a first body bias circuit coupled to drive first body regions to a first bias voltage in response to at least first bias values; a second body bias circuit coupled to drive second body regions to a second bias voltage in response to at least second bias values; a plurality of monitoring sections formed in a same substrate as the operational section, each configured to output a monitor value reflecting a different process variation effect on circuit performance.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 26, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lawrence T. Clark, Michael S. McGregor, Robert Rogenmoser, David A. Kidd, Augustine Kuo
  • Patent number: 8819603
    Abstract: A circuit can include a plurality of storage circuits, each having a pair of first conductivity type transistor having sources commonly connected to a first node, and gates and drains cross-coupled between first and second storage node; and a pair of second conductivity type transistor having sources commonly connected to a second node, and gates and drains cross-coupled between the first and second storage node; wherein each of the second conductivity type transistors comprises a screening region of the first conductivity type formed below the channel region and has a predetermined minimum dopant concentration.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 26, 2014
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Samuel Leshner
  • Patent number: 8811068
    Abstract: An integrated circuit can include SRAM cells, with pull-up transistors, pull-down transistors, and pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer. The screening region has a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer. The screening region can provide an enhanced body coefficient for the pull-up transistors to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region. Related methods are also disclosed.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: August 19, 2014
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally
  • Patent number: 8806395
    Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 12, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Samuel Leshner