Patents by Inventor Lawrence T. Clark

Lawrence T. Clark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8791718
    Abstract: The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs have a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: July 29, 2014
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Nathan D. Hindman, Dan Wheeler Patterson
  • Publication number: 20140204644
    Abstract: Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein.
    Type: Application
    Filed: March 19, 2014
    Publication date: July 24, 2014
    Applicant: Arizona Board of Regents for and on Behalf of Arizona State University
    Inventors: Satendra Kumar Maurya, Lawrence T. Clark
  • Patent number: 8787086
    Abstract: The present disclosure relates to inhibiting address transitions in unselected memory banks of solid state memory circuits. Bank selection and address gating circuitry may be used to provide a set of gated address signals to decode circuitry for each memory bank, such that the gated address signals associated with unselected memory banks are prevented from transitioning and the gated address signals associated with a selected memory bank are based on clocking in the status of address signals provided by memory control circuitry.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: July 22, 2014
    Assignee: The Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Giby Samson
  • Patent number: 8767445
    Abstract: Circuitry that includes static random access memory (SRAM) access circuitry and a group of SRAM memory cells is disclosed. A digital fingerprint of the group of SRAM memory cells is determined by using the SRAM access circuitry to force at least a portion of the group of SRAM memory cells into a metastable state and then releasing the portion of the SRAM memory cells. Each SRAM memory cell that was released then selects one of two stable states and the SRAM access circuitry provides a selection profile based on the selections. The digital fingerprint is based on the selection profile.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 1, 2014
    Assignee: Arizona Board of Regents for and on behalf of Arizone State University
    Inventors: Srivatsan Chellappa, Lawrence T. Clark
  • Patent number: 8732490
    Abstract: A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Marvell International Ltd.
    Inventors: Dennis M. O'Connor, Michael W. Morrow, Lawrence T. Clark
  • Patent number: 8717793
    Abstract: Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: May 6, 2014
    Assignee: Arizona Board of Regents, for and on Behalf of Arizona State University
    Inventors: Satendra Kumar Maurya, Lawrence T. Clark
  • Publication number: 20140119099
    Abstract: A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region.
    Type: Application
    Filed: October 31, 2013
    Publication date: May 1, 2014
    Applicant: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Lucian Shifren, Richard S. Roy
  • Patent number: 8713511
    Abstract: An integrated circuit having at least one array of circuit cells, each circuit cell having a plurality of transistors each performing a specified function, the transistors having predefined performance parameter margins for the specified function, the circuit cells designed by providing at least one operating condition for the circuit cell; providing a value of sigma over a predefined range; determining for each transistor, at least one variable transistor characteristic, which is defined by a semiconductor process that results in transistors having such transistor characteristics; providing an array of instances based upon the value of the sigma and using a design of experiments factorial calculation; providing a metric of interest by which to deter-nine pass/fail instances; extracting individual pass/fail instances for the metric of interest; and determining a yield for the array of circuit cells for the targeted operating condition.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: April 29, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lawrence T. Clark, Samuel Leshner
  • Publication number: 20140077854
    Abstract: This disclosure relates generally to sequential state elements (SSEs). More specifically, embodiments of flip-flops are disclosed, along with computerized methods and systems of designing the same. In one embodiment, the flip-flop includes a substrate and subcircuits that are formed on the substrate. The subcircuits provide subfunctions, wherein each of the subcircuits provides at least one of the subfunctions. More specifically, the subfunctions are provided in a sequential logical order by the subcircuits so that the flip-flop provides a flip-flop function. However, the subcircuits are interleaved out of the sequential logical order with respect to a corresponding subfunction provided by each of the subcircuits along a vector defined by the substrate. In this manner, interleaving the subcircuits along the vector of the substrate can provide separation between charge collection nodes without requiring increases in size. Thus, the flip-flop can be more compact and less expensive to manufacture.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 20, 2014
    Applicant: Arizona Board of Regents, a body corporated of the State of Arizona, acting for and on behalf of Ari
    Inventors: Lawrence T. Clark, Sandeep Shambhulingaiah, Sushil Kumar, Chandarasekaran Ramamurthy
  • Publication number: 20140049286
    Abstract: The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.
    Type: Application
    Filed: October 24, 2013
    Publication date: February 20, 2014
    Applicant: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Ariz
    Inventor: Lawrence T. Clark
  • Patent number: 8645878
    Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 4, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Samuel Leshner
  • Patent number: 8599623
    Abstract: An integrated circuit device can include a plurality of test elements, each comprising at least one first switch coupled between a node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and an output node; wherein the forced voltage node is coupled to receive a forced voltage substantially the same as a test voltage applied to the output node in a test mode.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 3, 2013
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T Clark, Richard S Roy
  • Patent number: 8488370
    Abstract: Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: July 16, 2013
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, Acting for and on behalf of Arizona State University
    Inventors: Sameer M. Venugopal, David R. Allee, Lawrence T Clark, Nazanin Darbanian
  • Patent number: 8489919
    Abstract: Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: July 16, 2013
    Assignee: Arizona Board of Regents
    Inventors: Lawrence T. Clark, Dan W. Patterson
  • Publication number: 20130154739
    Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
    Type: Application
    Filed: February 19, 2013
    Publication date: June 20, 2013
    Inventors: Lawrence T. Clark, Scott E. Thompson
  • Patent number: 8462565
    Abstract: Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. In one example, a method for providing an integrated circuit can comprise providing a memory cell coupled to a first bitline and to a second bitline, and at least one of (a) providing a read assist mechanism configured to couple to the memory cell via the first and second bitlines, or (b) providing a memory reset mechanism configured to couple to the memory cell via the first and second bitlines. Providing the memory cell can comprise providing a first transistor comprising a first threshold voltage, providing a second transistor comprising a second threshold voltage, and cross-coupling the first and second transistors of the memory cell together. A difference between the first and second threshold voltages can correspond to a logic state of the memory cell. Other embodiments, examples, and related methods are also disclosed herein.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: June 11, 2013
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, Acting for and on behalf of Arizona State University
    Inventors: Sameer M. Venugopal, David R. Allee, Lawrence T. Clark
  • Patent number: 8461875
    Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 11, 2013
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Lawrence T. Clark
  • Publication number: 20130111282
    Abstract: Systems and methods for performing parallel test operations on Static Random Access Memory (SRAM) cells are disclosed. In general, each parallel test operation is a test operation performed on a block of the SRAM cells in parallel, or simultaneously. In one embodiment, the SRAM cells are arranged into multiple rows and multiple columns where the columns are further arranged into one or more column groups. The block of the SRAM cells for each parallel test operation includes SRAM cells in two or more of the rows, SRAM cells in two or more columns in the same column group, or both SRAM cells in two or more rows and SRAM cells in two or more columns in the same column group.
    Type: Application
    Filed: July 19, 2011
    Publication date: May 2, 2013
    Inventors: Lawrence T. Clark, Yu Cao
  • Patent number: 8400219
    Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: March 19, 2013
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Scott E. Thompson
  • Patent number: 8397133
    Abstract: Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: March 12, 2013
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Dan W. Patterson, Xiaoyin Yao, David Pettit, Rahul Shringarpure