Abstract: Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.

Abstract: A method includes providing power to on-die combinatorial circuitry of an integrated circuit (IC) from an external power supply regulator during an active mode of the IC. A state of the on-die combinatorial circuitry of the IC is moved into on-die storage of the IC. Power to the on-die combinational circuitry is disabled during a low power mode of the IC by disrupting power supplied from the external power supply regulator to the IC. A power feedback signal from an internal portion of the IC is provided to the external power supply regulator.

Abstract: An imaging system includes a photocell circuit. The photocell circuit includes a photodetector circuit. The photodetector circuit includes an input configured to receive incident light. A first terminal communicates with a sample node. A second terminal communicates with a monitor node. A sampling circuit is configured to drive the sample node to a first reset value at a first time in response to a first reset signal. The sampling circuit allows the first reset value to decay at a second time subsequent to the first time. A monitor circuit is configured to drive the monitor node to a second reset value at the first time in response to a second reset signal. The monitor circuit allows the second reset value to decay at the second time. The monitor circuit detects a third time when the monitor node decays to a predetermined stop value subsequent to the second time.

Abstract: The present invention provides a radiation hardened flip-flop formed from a modified temporal latch and a modified dual interlocked storage cell (DICE) latch. The temporal latch is configured as the master latch and provides four output storage nodes, which represent outputs of the temporal latch. The DICE latch is configured as the slave latch and is made of two cross-coupled inverter latches, which together provide four DICE storage nodes. The four outputs of the temporal latch are used to write the four DICE storage nodes of the DICE latch. The temporal latch includes at least one feedback path that includes a delay element, which provides a delay.

Abstract: The present invention relates to radiation hardening by design (RHBD), which employs layout and circuit techniques to mitigate the damaging effects of ionizing radiation. Reverse body biasing (RBB) of N-type metal-oxide-semiconductor (NMOS) transistors may be used to counteract the effects of trapped positive charges in isolation oxides due to ionizing radiation. In a traditional MOS integrated circuit, input/output (I/O) circuitry may be powered using an I/O power supply voltage, and core circuitry may be powered using a core power supply voltage, which is between the I/O power supply voltage and ground. However, in one embodiment of the present invention, the core circuitry is powered using a voltage difference between the core power supply voltage and the I/O power supply voltage. The bodies of NMOS transistors in the core circuitry are coupled to ground; therefore, a voltage difference between the core power supply voltage and ground provides RBB.

Abstract: The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Abstract: A multi-context register file for use in a multi-threaded processor includes at least one multi-context register file cell having internal routing functionality.

Abstract: Imaging system having a sensor array with photocells that permit the monitoring of light levels while the sensor is exposed to a scene, and the ability to accurately avoid saturation on a per column, row, or array basis. The sensor array supports variable dynamic range by allowing variable integration times for different columns or rows of the array, thereby improving image quality of a scene in which there are both strong and weak light areas. In one embodiment, the photocell includes a parasitic multi-emitter bipolar junction transistor (BJT) acting as a photodetector. The parasitic device is part of a saturation detection circuit and also supports an electronic shutter mechanism. The parasitic BJT also permits increased sensitivity over some previous CMOS approaches. The photocell design is also spatially efficient, using in one embodiment only four MOSFETs in addition to the parasitic BJT.

Abstract: The present invention provides a PLA architecture where the AND plane is implemented with NAND logic. The OR plane may be implemented with various logic, but in one embodiment, the OR plane is implemented with NOR logic. The AND plane may have multiple sequential stages providing hierarchical NAND logic. The NAND logic may be broken into a hierarchy of NAND logic blocks. Each NAND logic block may include one or more series-connected NAND transistor stacks. Each transistor in the transistor stack may receive an input signal representing the product of a PLA clock signal and either a direct PLA input or the complement thereof. As such, the PLA clock is inherently integrated with the input signals that drive the various transistors of the NAND transistor stacks.

Abstract: A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.

Abstract: A write circuit structure may be used to transfer data between global bit lines and local bit lines of a cache. The write circuit structure located between the hierarchical bit lines may be buffers in parallel with P-channel devices in one embodiment or cross-coupled P-channel and N-channel devices in another embodiment.

Abstract: A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.

Abstract: Circuitry gates the power supply to limit standby power in an integrated circuit. The IR drop through clamps may be compensated using a regulator feedback signal to improve the power performance and allow the power supply regulator to supply the best quality power signals possible.

Abstract: The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Abstract: A multi-context register file for use in a multi-threaded processor includes at least one multi-context register file cell having internal routing functionality.

Abstract: An integrated circuit includes power gating circuits for coupling an associated circuit block with a power supply voltage. The power gating circuits also generate power consumption measurements for the associated circuit blocks. A power manager for the integrated circuit may manage the overall power consumption of the integrated circuit and may individually turn on and off the circuit blocks using the power gating circuits.

Abstract: A memory driver architecture and associated methods are generally described.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential.

Abstract: A processor system having cache array for storing virtual tag information and physical tag information and corresponding comparators associated with the array to determine cache-hits. Information from the virtual tag array and the physical tag array may be accessed together.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.