Abstract: A processor having an L1 cache memory that may use a compare circuit to determine matches of stored tag information against an address and gate sense amps of the cache memory with a cache-hit signal.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

Abstract: An integrated circuit having a microprocessor core and a memory block that may operate at different voltages. A voltage regulator, either external to the integrated circuit or designed as part of the integrated circuit, generates the two voltages. The operating voltage for the microprocessor core is selected to satisfy power and performance criteria while the operating voltage for the memory block is set to provide acceptable noise margins and maintain stability of the memory cells within the memory block.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a sense amp connected to a plurality of bit lines with bit line transistors. Each of the bit line transistors may be connected to a sense amp enable transistor so that together, the coupling and sense amp enable transistors connect the sense amp to a power supply voltage.

Abstract: An integrated circuit having CMOS transistors processed with different gate-oxide thicknesses. The transistors having the thinner gate-oxide may be used to generate data values that may be stored by the transistors having the thicker gate-oxides. The thicker gate-oxides may reduce gate leakage currents during a system standby mode.

Abstract: An integrated circuit having CMOS domino logic arranged in multistages or a tree structure. The multistage cells and addressing structure may have applications in a decoder and reduce the number of cells being precharged and reduce the operating power.

Abstract: Embodiments of the invention are disclosed that include a low power memory and a low power data path.

Abstract: An integrated circuit having CMOS transistors processed with different gate-oxide thicknesses. The transistors having the thinner gate-oxide may be used to generate data values that may be stored by the transistors having the thicker gate-oxides. The thicker gate-oxides may reduce gate leakage currents during a system standby mode.

Abstract: Embodiments are disclosed that include a low power memory and/or a low power data path. One particular embodiment, for example, includes a technique to reduce power consumption. In one particular embodiment, for example, a grouping of bits, such as a 32-bit word, for example, is stored in inverted form if more than half of the bits have a bit value of logic “1” rather than logic “0.” Likewise, in this embodiment, if more than half of the bits have a bit value of logic “0” rather than logic “1,” then the grouping of bits is not stored in inverted form.

Abstract: Imaging system having a sensor array with photocells that permit the monitoring of light levels while the sensor is exposed to a scene, and the ability to accurately avoid saturation on a per column, row, or array basis. The sensor array supports variable dynamic range by allowing variable integration times for different columns or rows of the array, thereby improving image quality of a scene in which there are both strong and weak light areas. In one embodiment, the photocell includes a parasitic multi-emitter bipolar junction transistor (BJT) acting as a photodetector. The parasitic device is part of a saturation detection circuit and also supports an electronic shutter mechanism. The parasitic BJT also permits increased sensitivity over some previous CMOS approaches. The photocell design is also spatially efficient, using in one embodiment only four MOSFETs in addition to the parasitic BJT.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide alternately activateable circuit configurations. The output buffer is adapted to couple to separate voltage supply voltage level ports and is further adapted to switch between the alternately activateable circuit configurations. The respective alternately activateable circuit configurations are respectively specifically adapted for interoperating with other integrated circuit chips, the respective threshold voltage levels of the semiconductor devices of different other integrated circuit chips being different.

Abstract: An integrated circuit having a microprocessor core and a memory block that may operate at different voltages. A voltage regulator, either external to the integrated circuit or designed as part of the integrated circuit, generates the two voltages. The operating voltage for the microprocessor core is selected to satisfy power and performance criteria while the operating voltage for the memory block is set to provide acceptable noise margins and maintain stability of the memory cells within the memory block.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit comprises a first stage that provides differential outputs in one mode and substantially equal outputs in another mode.

Abstract: Imaging system having a sensor array with photocells that permit the monitoring of light levels while the sensor is exposed to a scene, and the ability to accurately avoid saturation on a per column, row, or array basis. The sensor array supports variable dynamic range by allowing variable integration times for different columns or rows of the array, thereby improving image quality of a scene in which there are both strong and weak light areas. In one embodiment, the photocell includes a parasitic multi-emitter bipolar junction transistor (BJT) acting as a photodetector. The parasitic device is part of a saturation detection circuit and also supports an electronic shutter mechanism. The parasitic BJT also permits increased sensitivity over some previous CMOS approaches. The photocell design is also spatially efficient, using in one embodiment only four MOSFETs in addition to the parasitic BJT.

Abstract: In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Abstract: In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.

Abstract: A first plurality of registers are daisy chained together with each register associated with a particular cache line. Similarly, a second plurality of registers are daisy chained together with each register associated with a cache line. The first daisy chain defines a fill order of cache lines and the second daisy chain defines a lock order for the cache lines.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide circuit configurations. The output buffer is adapted to couple to separate voltage supply voltage level ports and is further adapted to switch between the circuit configurations. The respective circuit configurations are respectively specifically adapted for interoperating with other integrated circuit chips, the respective threshold voltage levels of the semiconductor devices of different other integrated circuit chips being different.