Patents by Inventor Leathen Shi
Leathen Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140166982Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.Type: ApplicationFiled: December 18, 2012Publication date: June 19, 2014Applicant: International Business Machines CorporationInventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
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Publication number: 20140166983Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.Type: ApplicationFiled: August 26, 2013Publication date: June 19, 2014Applicant: International Business Machines CorporationInventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
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Patent number: 8637381Abstract: Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.Type: GrantFiled: October 17, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Effendi Leobandung, Dae-Gyu Park, Shom S. Ponoth, Zhibin Ren, Ghavam G. Shahidi, Leathen Shi
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Patent number: 8586426Abstract: Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.Type: GrantFiled: August 3, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Robert H. Dennard, Marwan H. Khater, Leathen Shi, Jeng-Bang Yau
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Publication number: 20130196483Abstract: Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect.Type: ApplicationFiled: September 5, 2012Publication date: August 1, 2013Applicant: International Business Machines CorporationInventors: Robert H. Dennard, Alfred Grill, Effendi Leobandung, Deborah A. Neumayer, Dea-Gyu Park, Ghavam G. Shahidi, Leathen Shi
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Publication number: 20130193445Abstract: Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect.Type: ApplicationFiled: January 26, 2012Publication date: August 1, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Dennard, Alfred Grill, Effendi Leobandung, Deborah A. Neumayer, Dea-Gyu Park, Ghavam G. Shahidi, Leathen Shi
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Patent number: 8492838Abstract: Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.Type: GrantFiled: November 16, 2009Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Robert H. Dennard, Marwan H. Khater, Leathen Shi, Jeng-Bang Yau
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Publication number: 20130105981Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles F. Musante, BethAnn Rainey, Leathen Shi, Edmund J. Sprogis, Cornelia K. Tsang
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Publication number: 20130093039Abstract: Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.Type: ApplicationFiled: October 17, 2011Publication date: April 18, 2013Applicant: International Business Machines CorporationInventors: EFFENDI LEOBANDUNG, Dae-Gyu Park, Shom S. Ponoth, Zhibin Ren, Ghavam G. Shahidi, Leathen Shi
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Patent number: 8408262Abstract: An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded.Type: GrantFiled: October 8, 2009Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventors: Dechao Guo, Fei Liu, Leathen Shi, Keith Kwong Hon Wong
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Publication number: 20120312452Abstract: An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded.Type: ApplicationFiled: August 22, 2012Publication date: December 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Fei Liu, Leathen Shi, Keith Kwong Hon Wong
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Publication number: 20120302039Abstract: Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.Type: ApplicationFiled: August 3, 2012Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Dennard, Marwan H. Khater, Leathen Shi, Jeng-Bang Yau
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Publication number: 20120112309Abstract: A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.Type: ApplicationFiled: January 16, 2012Publication date: May 10, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Dennard, David R. Greenberg, Amlan Majumdar, Leathen Shi, Jeng-Bang Yau
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Patent number: 8030145Abstract: A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.Type: GrantFiled: January 8, 2010Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Leland Chang, Brian L. Ji, Arvind Kumar, Amlan Majumdar, Katherine Saenger, Leathen Shi, Jeng-Bang Yau
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Patent number: 8017499Abstract: A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.Type: GrantFiled: May 22, 2008Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Jack O. Chu, Kern Rim, Leathen Shi
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Publication number: 20110171792Abstract: A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.Type: ApplicationFiled: January 8, 2010Publication date: July 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Brian L. Ji, Arvind Kumar, Amlan Majumdar, Katherine Saenger, Leathen Shi, Jeng-Bang Yau
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Publication number: 20110115021Abstract: Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.Type: ApplicationFiled: November 16, 2009Publication date: May 19, 2011Applicant: International Business Machines CorporationInventors: Robert H. Dennard, Marwan H. Khater, Leathen Shi, Jeng-Bang Yau
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Publication number: 20110083786Abstract: An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded.Type: ApplicationFiled: October 8, 2009Publication date: April 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Fei Liu, Leathen Shi, Keith Kwong Hon Wong
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Patent number: 7897480Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. Similarly, a method for forming thin to ultra-thin strain Si, SiC, or SiC/Si layers directly on insulator substrates having a strain content in the range of about 1-5% is further described.Type: GrantFiled: April 23, 2007Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Jack O. Chu, Alexander Reznicek, Philip A. Saunders, Leathen Shi
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Patent number: 7767546Abstract: A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.Type: GrantFiled: January 12, 2009Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Robert H. Dennard, David R. Greenberg, Amian Majumdar, Leathen Shi, Jeng-Bang Yau