Patents by Inventor Lee Teck Kheng

Lee Teck Kheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11633236
    Abstract: A system and an apparatus for guiding an instrument may be provided, the apparatus comprising a main body; a holding member for holding an instrument, the holding member coupled to the main body; and one or more actuating members configured to effect movement of the holding member such that said movement of the holding member is capable of providing rotational movement of an instrument about a pivot point external the apparatus. The holding member may preferably be configured to co-operate with a compliance device, said compliance device capable of holding the instrument.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: April 25, 2023
    Assignee: INVIVO MEDICAL PTE LTD
    Inventors: Foo Soo Leong, Ng Ka Wei, Goh Jin Quan, Ting Poh Hua, Lee Teck Kheng, Wu Qinghui, Chiong Edmund, Esuvaranathan Kesavan
  • Publication number: 20210059768
    Abstract: A system and an apparatus for guiding an instrument may be provided, the apparatus comprising a main body; a holding member for holding an instrument, the holding member coupled to the main body; and one or more actuating members configured to effect movement of the holding member such that said movement of the holding member is capable of providing rotational movement of an instrument about a pivot point external the apparatus. The holding member may preferably be configured to co-operate with a compliance device, said compliance device capable of holding the instrument.
    Type: Application
    Filed: October 1, 2020
    Publication date: March 4, 2021
    Inventors: Foo Soo Leong, Ng Ka Wei, Goh Jin Quan, Ting Poh Hua, Lee Teck Kheng, Wu Qinghui, Chiong Edmund, Esuvaranathan Kesavan
  • Patent number: 10835323
    Abstract: A system and an apparatus for guiding an instrument may be provided, the apparatus comprising a main body; a holding member for holding an instrument, the holding member coupled to the main body; and one or more actuating members configured to effect movement of the holding member such that said movement of the holding member is capable of providing rotational movement of an instrument about a pivot point external the apparatus. The holding member may preferably be configured to co-operate with a compliance device, said compliance device capable of holding the instrument.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: November 17, 2020
    Assignees: Institute of Technical Education, National University Hospital (Singapore) Pte Ltd., National University of Singapore
    Inventors: Foo Soo Leong, Ng Ka Wei, Goh Jin Quan, Ting Poh Hua, Lee Teck Kheng, Wu Qinghui, Chiong Edmund, Esuvaranathan Kesavan
  • Publication number: 20160206383
    Abstract: A system and an apparatus for guiding an instrument may be provided, the apparatus comprising a main body; a holding member for holding an instrument, the holding member coupled to the main body; and one or more actuating members configured to effect movement of the holding member such that said movement of the holding member is capable of providing rotational movement of an instrument about a pivot point external the apparatus. The holding member may preferably be configured to co-operate with a compliance device, said compliance device capable of holding the instrument.
    Type: Application
    Filed: August 28, 2013
    Publication date: July 21, 2016
    Applicants: Institute of Technical Education, National University Hospital (S) Pte Ltd., National University of Singapore
    Inventors: Foo Soo Leong, Ng Ka Wei, Goh Jin Quan, Ting Poh Hua, Lee Teck Kheng, Wu Qinghui, Chiong Edmund, Esuvaranathan Kesavan
  • Publication number: 20110019372
    Abstract: Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.
    Type: Application
    Filed: October 6, 2010
    Publication date: January 27, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Lee Teck Kheng
  • Patent number: 7572670
    Abstract: The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circuit traces and also contacting the die. The invention also includes methods of forming semiconductor packages. Such methods can include provision of a construction comprising an electrically conductive layer on a masking material. The layer has a first surface facing the masking material and a second surface in opposing relation to the first surface. The masking material is patterned to form openings extending to the first surface of the layer. The layer is then patterned. Subsequently, an integrated circuit die is provided over the second surface of the layer.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: August 11, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Lee Teck Kheng
  • Publication number: 20090057912
    Abstract: Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.
    Type: Application
    Filed: September 28, 2007
    Publication date: March 5, 2009
    Applicant: Micron Technology, Inc.
    Inventor: Lee Teck Kheng
  • Patent number: 7262499
    Abstract: The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circuit traces and also contacting the die. The invention also includes methods of forming semiconductor packages. Such methods can include provision of a construction comprising an electrically conductive layer on a masking material. The layer has a first surface facing the masking material and a second surface in opposing relation to the first surface. The masking material is patterned to form openings extending to the first surface of the layer. The layer is then patterned. Subsequently, an integrated circuit die is provided over the second surface of the layer.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: August 28, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Lee Teck Kheng
  • Patent number: 6913952
    Abstract: The invention encompasses methods of preparing interposers for utilization in semiconductor packages. The invention includes a method in which an interposer substrate having a surface and a conductive layer extending over the surface is provided. Pads are formed on the conductive layer by plating a conductive material on the conductive layer while using the conductive layer as an electrical connection to a power source and without utilizing conductive busses, other than the conductive layer. Subsequent to the formation of the pads, the conductive layer is patterned into circuit traces. Methodology of the present invention can be utilized for, for example, forming board-on-chip constructions.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: July 5, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Stephen F. Moxham, Lee Teck Kheng, Steve Thummel