Patents by Inventor Leeor Peled
Leeor Peled has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922220Abstract: Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution.Type: GrantFiled: April 16, 2019Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Mohammad R. Haghighat, Kshitij Doshi, Andrew J. Herdrich, Anup Mohan, Ravishankar R. Iyer, Mingqiu Sun, Krishna Bhuyan, Teck Joo Goh, Mohan J. Kumar, Michael Prinke, Michael Lemay, Leeor Peled, Jr-Shian Tsai, David M. Durham, Jeffrey D. Chamberlain, Vadim A. Sukhomlinov, Eric J. Dahlen, Sara Baghsorkhi, Harshad Sane, Areg Melik-Adamyan, Ravi Sahita, Dmitry Yurievich Babokin, Ian M. Steiner, Alexander Bachmutsky, Anil Rao, Mingwei Zhang, Nilesh K. Jain, Amin Firoozshahian, Baiju V. Patel, Wenyong Huang, Yeluri Raghuram
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Patent number: 11720364Abstract: Disclosed Methods, Apparatus, and articles of manufacture to dynamically enable and/or disable prefetchers are disclosed. An example apparatus include an interface to access telemetry data, the telemetry data corresponding to a counter of a core in a central processing unit, the counter corresponding to a first phase of a workload executed at the central processing unit; a prefetcher state selector to select a prefetcher state for a subsequent phase based on the telemetry data; and the interface to instruct the core in the central processing unit to operate in the subsequent phase according to the prefetcher state.Type: GrantFiled: September 25, 2020Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Hanna Alam, Leeor Peled, Refael Mizrahi, Amir Leibovitz, Jonathan Beimel, James Hermerding, II, Gilad Olswang, Michal Moran, Moran Peri, Ido Karavany, Sudheer Nair, Hadas Beja, Avishai Wagner, Ronen Laperdon
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Publication number: 20210263779Abstract: Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution.Type: ApplicationFiled: April 16, 2019Publication date: August 26, 2021Applicant: Intel CorporationInventors: Mohammad R. Haghighat, Kshitij Doshi, Andrew J. Herdrich, Anup Mohan, Ravishankar R. Iyer, Mingqiu Sun, Krishna Bhuyan, Teck Joo Goh, Mohan J. Kumar, Michael Prinke, Michael Lemay, Leeor Peled, Jr-Shian Tsai, David M. Durham, Jeffrey D. Chamberlain, Vadim A. Sukhomlinov, Eric J. Dahlen, Sara Baghsorkhi, Harshad Sane, Areg Melik-Adamyan, Ravi Sahita, Dmitry Yurievich Babokin, Ian M. Steiner, Alexander Bachmutsky, Anil Rao, Mingwei Zhang, Nilesh K. Jain, Amin Firoozshahian, Baiju V. Patel, Wenyong Huang, Yeluri Raghuram
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Publication number: 20210232426Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.Type: ApplicationFiled: November 10, 2020Publication date: July 29, 2021Applicant: Intel CorporationInventors: Andrew Herdrich, Ian Steiner, Leeor Peled, Michael Prinke, Eylon Toledano
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Publication number: 20210011726Abstract: Disclosed Methods, Apparatus, and articles of manufacture to dynamically enable and/or disable prefetchers are disclosed. An example apparatus include an interface to access telemetry data, the telemetry data corresponding to a counter of a core in a central processing unit, the counter corresponding to a first phase of a workload executed at the central processing unit; a prefetcher state selector to select a prefetcher state for a subsequent phase based on the telemetry data; and the interface to instruct the core in the central processing unit to operate in the subsequent phase according to the prefetcher state.Type: ApplicationFiled: September 25, 2020Publication date: January 14, 2021Inventors: Hanna Alam, Leeor Peled, Refael Mizrahi, Amir Leibovitz, Jonathan Beimel, James Hermerding, II, Gilad Olswang, Michal Moran, Moran Peri, Ido Karavany, Sudheer Nair, Hadas Beja, Avishai Wagner, Ronen Laperdon
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Patent number: 10866834Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.Type: GrantFiled: March 29, 2019Date of Patent: December 15, 2020Assignee: Intel CorporationInventors: Andrew Herdrich, Ian Steiner, Leeor Peled, Michael Prinke, Eylon Toledano
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Publication number: 20200310865Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Andrew Herdrich, Ian Steiner, Leeor Peled, Michael Prinke, Eylon Toledano
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Patent number: 10725755Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.Type: GrantFiled: June 6, 2017Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffrey J. Cook, Omar M. Shaikh, Suresh Srinivas
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Patent number: 10157136Abstract: A processor includes a front end to decode instructions, an execution unit to execute instructions, multiple caches at different cache hierarchy levels, a pipelined prefetcher, and a retirement unit to retire instructions. The prefetcher includes circuitry to receive a demand request for data at a first address within a first line in a memory and, in response, to provide the data at the first address to the execution unit for consumption, to prefetch a second line at a first offset distance from the first line into a mid-level cache, and to prefetch a third line at a second offset distance from the second line into a last-level cache. The prefetcher includes circuitry to prefetch, in response to another demand request, the third line into the mid-level cache, and a fourth line into the last-level cache. The prefetcher enforces minimum or maximum offset distances between prefetched data streams.Type: GrantFiled: March 31, 2016Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Leeor Peled, Joseph Nuzman, Larisa Novakovsky
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Publication number: 20180173534Abstract: A processor may include a decoder to decode a first instance of a branch instruction for which the resolved branch direction is data dependent and add results of the decoding to a stream of decoded instructions for execution. The processor may include a code generator to inject, into the stream of decoded instructions, branch resolution code to resolve the branch condition for a second instance of the branch instruction following the first instance at a predetermined look-ahead distance. The processor may include an execution unit to execute the branch resolution code, storing an indication of the resolved branch direction for the second instance in an entry of a prediction queue for the branch instruction. The processor may include a branch predictor to receive the second instance of the branch instruction, and output the resolved branch direction as the predicted branch direction for the second instance of the branch instruction.Type: ApplicationFiled: December 20, 2016Publication date: June 21, 2018Inventors: Leeor Peled, Gadi Haber, Yiannakis Sazeides
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Publication number: 20180060049Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.Type: ApplicationFiled: June 6, 2017Publication date: March 1, 2018Inventors: DAVID J. SAGER, RUCHIRA SASANKA, RON GABOR, SHLOMO RAIKIN, JOSEPH NUZMAN, LEEOR PELED, JASON A. DOMER, HO-SEOP KIM, YOUFENG WU, KOICHI YAMADA, TIN-FOOK NGAI, HOWARD H. CHEN, JAYARAM BOBBA, JEFFREY J. COOK, OMAR M. SHAIKH, SURESH SRINIVAS
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Publication number: 20170286304Abstract: A processor includes a front end to decode instructions, an execution unit to execute instructions, multiple caches at different cache hierarchy levels, a pipelined prefetcher, and a retirement unit to retire instructions. The prefetcher includes circuitry to receive a demand request for data at a first address within a first line in a memory and, in response, to provide the data at the first address to the execution unit for consumption, to prefetch a second line at a first offset distance from the first line into a mid-level cache, and to prefetch a third line at a second offset distance from the second line into a last-level cache. The prefetcher includes circuitry to prefetch, in response to another demand request, the third line into the mid-level cache, and a fourth line into the last-level cache. The prefetcher enforces minimum or maximum offset distances between prefetched data streams.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Leeor Peled, Joseph Nuzman, Larisa Novakovsky
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Patent number: 9672019Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.Type: GrantFiled: December 25, 2010Date of Patent: June 6, 2017Assignee: Intel CorporationInventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas
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Publication number: 20110167416Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.Type: ApplicationFiled: December 25, 2010Publication date: July 7, 2011Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas