Patents by Inventor Leilei CHENG

Leilei CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961848
    Abstract: Disclosed are a display substrate and a manufacturing method therefor, and a display device. The display substrate comprises: a substrate base, and an active layer, a gate insulating layer, a first metal film layer, an interlayer insulating layer, a second metal film layer, and a passivation layer stacked in sequence on the substrate base. The first metal film layer comprises a pattern of a gate and a gate line. The second metal film layer comprises a pattern of a source/drain and a data line. The gate line and the data line are partially arranged opposite to each other. An oxide metal layer is provided on the surface of the side of the region of the gate line opposite to the data line facing the data line.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 16, 2024
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jun Liu, Liangchen Yan, Bin Zhou, Yadong Liang, Ning Liu, Leilei Cheng, Jingang Fang
  • Publication number: 20240090207
    Abstract: A semiconductor structure includes a substrate and a word line structure. The substrate includes an array region and a peripheral region. The word line structure includes a first conductive layer disposed on the substrate, and the first conductive layer penetrates the array region and extends to the peripheral region in a first direction. In a normal direction of the substrate, a height of the first conductive layer on a surface of the peripheral region is higher than a height of the first conductive layer on a surface of the array region.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Ran LI, Biao Zang, Chih-Cheng Lin, Leilei Duan
  • Patent number: 11930677
    Abstract: A display panel and a fabricating method thereof, and a displaying device. The display panel includes a substrate, a resistance reducing trace, an inter-layer-medium layer and a signal line. The substrate is divided into a plurality of sub-pixel regions and a pixel separating region. The resistance reducing trace is provided on the pixel separating region of the substrate. The inter-layer-medium layer is provided on the substrate, and the inter-layer-medium layer has an opening exposing the resistance reducing trace. The signal line is provided within the opening, the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 12, 2024
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongchao Huang, Can Yuan, Liusong Ni, Chao Wang, Jiawen Song, Zhiwen Luo, Jun Liu, Leilei Cheng, Qinghe Wang, Tao Sun
  • Patent number: 11882716
    Abstract: A method for manufacturing a display panel includes: sequentially forming a conductive pattern, a light-emitting layer and a cathode layer on a substrate. The conductive pattern is formed by a one-time patterning process, and includes an auxiliary electrode layer. In a direction parallel to the substrate, both the first protective electrode and the second protective electrode in the auxiliary electrode layer extend over the metal electrode, a second orthographic projection of the second protective electrode on the substrate is within a first orthographic projection of the first protective electrode on the substrate, and an outer boundary of the second orthographic projection is staggered from an outer boundary of the first orthographic projection. The cathode layer is in contact with the first protective electrode and a sidewall of the metal electrode.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: January 23, 2024
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yang Zhang, Ning Liu, Bin Zhou, Leilei Cheng, Liangchen Yan, Jun Liu, Qinghe Wang, Tao Sun, Zhiwen Luo
  • Publication number: 20230380215
    Abstract: The disclosure relates to the technical field of display, in particular to a displaying substrate, a manufacturing method thereof and a display panel. The displaying substrate comprises a passivation layer (28) and a flat layer (29) covering the passivation layer (28), wherein the flat layer (29) comprises a first flat via hole and a plurality of second flat via holes, the passivation layer (28) comprises a first passivation via hole, and the first flat via hole and the first passivation via hole form a first sleeve hole (31); and the hole depth of the first flat via hole is smaller than that of each second flat via hole, and the hole depth of the first passivation via hole is greater than or equal to the difference between the maximum hole depth of all the second flat via holes and the hole depth of the first flat via hole.
    Type: Application
    Filed: February 24, 2021
    Publication date: November 23, 2023
    Inventors: Leilei CHENG, Yongchao HUANG, Qinghe WANG, Yang ZHANG, Bin ZHOU
  • Publication number: 20230337466
    Abstract: A display substrate and a manufacture method thereof, and a display apparatus are provided. The base substrate includes a base substrate, the base substrate is provided with a plurality of pixels in an array, one pixel includes a plurality of sub-pixels, each sub-pixel includes a light-emitting device and a pixel circuit driving the light-emitting device to emit light, and the pixel circuit includes a storage capacitor, a driving transistor and a data writing transistor; the first electrode of the driving transistor receives a first power voltage; the second electrode of the driving transistor is connected to the light-emitting device; at least part of the plurality of sub-pixels includes a first via hole, and the first electrode of the data writing transistor is electrically connected to the gate electrode of the driving transistor and the active layer of the data writing transistor through the first via hole.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 19, 2023
    Inventors: Leilei CHENG, Cheng XU, Jie LIU, Chunjie XU
  • Patent number: 11737305
    Abstract: A light-emitting device includes: an anode disposed on a base, and a cathode disposed on a side of the anode facing away from the base. The anode includes a light-reflecting sub-electrode and a light-transmitting sub-electrode located on a surface of the light-reflecting sub-electrode facing away from the base, and an orthographic projection of the light-transmitting sub-electrode on the base is located within a range of an orthographic projection of the light-reflecting sub-electrode on the base. The light-reflecting sub-electrode includes a metal pattern and a metal oxide pattern, and the metal oxide pattern is located in at least part of a region around the metal pattern.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 22, 2023
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Song, Ce Zhao, Yuankui Ding, Ming Wang, Ning Liu, Leilei Cheng, Junlin Peng, Yingbin Hu, Liusong Ni
  • Publication number: 20230133139
    Abstract: Disclosed are a preparation method thereof, a display panel, and a display device. The drive backboard comprises: a pixel circuit disposed on a base substrate; an anode disposed on a side of the pixel circuit facing away from the base substrate and electrically connected to the pixel circuit; and a first insulating layer disposed between the base substrate and the anode; the first insulating layer is provided with a groove surrounding the pixel circuit, the anode covers the first insulating layer, and an edge of the anode extends to an inner wall of the groove.
    Type: Application
    Filed: December 30, 2020
    Publication date: May 4, 2023
    Inventors: Yang ZHANG, Liangchen YAN, Bin ZHOU, Qinghe WANG, Leilei CHENG, Wei LI, Tao SUN
  • Patent number: 11559592
    Abstract: A sterilization structure, a sterilization board, and a display device are disclosed. The sterilization structure includes an active layer, wherein, one surface of the active layer has an exposed region, and a material of the active layer includes a laser-induced graphene material.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: January 24, 2023
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Guangyao Li, Luke Ding, Leilei Cheng, Yingbin Hu, Jingang Fang, Ning Liu, Qinghe Wang, Dongfang Wang, Liangchen Yan
  • Patent number: 11537016
    Abstract: A method of manufacturing an array substrate is provided, which comprises: forming a first metal layer and an insulating layer in sequence on a base substrate, the insulating layer covering the first metal layer; forming an etch barrier layer on the insulating layer; etching the etching barrier layer and the insulating layer multiple times, wherein an effective blocking area of the etching barrier layer decreases successively in each etching to form a connection hole penetrating the insulating layer, the connection hole includes a plurality of via holes connected in sequence, and a slope angle of a hole wall of each via hole is smaller than a preset slope angle; and forming a second metal layer, the second metal layer being connected to the first metal layer through the connection hole.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 27, 2022
    Assignees: HEFEI XINSHENG OPTOFT FCTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Leilei Cheng, Jingang Fang, Luke Ding, Jun Liu, Wei Li, Bin Zhou
  • Patent number: 11469394
    Abstract: The present invention relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a first electrode layer. The first electrode layer may include an indium tin oxide layer and a planarization layer. The indium tin oxide layer is disposed on a substrate and includes indium tin oxide particles; the planarization layer is disposed on a side of the indium tin oxide layer away from the substrate, and fills at least part of gaps between the indium tin oxide particles, and the planarization layer can conduct electricity.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: October 11, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Leilei Cheng, Tongshang Su, Qinghe Wang, Guangyao Li, Wei Song, Ning Liu, Yang Zhang, Yongchao Huang
  • Patent number: 11462602
    Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a first signal line on the base substrate; a first buffer layer provided on the base substrate and covering the first signal line; a second signal line on a side of the first buffer layer facing away from the base substrate; a first insulating layer provided on the base substrate and covering the second signal line; and a thin film transistor on a side of the first insulating layer facing away from the base substrate, the thin film transistor including a gate electrode, a source electrode and a drain electrode. A thickness of the first signal line is greater than that of the gate electrode, and a thickness of the second signal line is greater than that of the source electrode or the drain electrode.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: October 4, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Yongchao Huang, Jun Cheng, Dongfang Wang, Jun Liu, Leilei Cheng, Liangchen Yan
  • Publication number: 20220262890
    Abstract: A display substrate includes: a base; a cathode power line disposed on the base and located in the peripheral region; a first insulating layer located on a side of a layer in which the cathode power line is located away from the base and having first via hole(s); a cathode layer located on the first insulating layer and electrically connected to the cathode power line through the first via hole(s); and spacer(s) located on a side of the cathode layer proximate to the base, a spacer covering at least a side wall of a first via hole, a thickness of a portion of the spacer covering the side wall decreasing along the side wall and in a direction pointing from an end of the side wall proximate to the base toward an end of the side wall of the first via hole away from the base.
    Type: Application
    Filed: February 9, 2021
    Publication date: August 18, 2022
    Applicants: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Leilei CHENG, Yongqian LI, Dacheng ZHANG
  • Publication number: 20220255036
    Abstract: A display panel includes: a plurality of pixel units on a side of a substrate, with each pixel unit including a light emitting device which includes a first electrode, a light emitting layer and a second electrode in sequence on the side of the substrate; and an auxiliary electrode layer on a side of the pixel units distal to the substrate and including light-transmitting regions and electrode regions, with an orthogonal projection of a corresponding light-transmitting region on the substrate at least covering that of the light emitting layer on the substrate, each light-transmitting region including a transparent structure, each electrode region including an auxiliary electrode, and the auxiliary electrode being electrically connected to the second electrode. A material of the auxiliary electrode includes a metal. A material of the transparent structure includes a metal oxide. The metal oxide and the metal have a same kind of element.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 11, 2022
    Inventor: Leilei CHENG
  • Patent number: 11398507
    Abstract: An array substrate includes an insulation layer and one or more stepped holes each penetrating through the insulation layer in a direction perpendicular to the insulation layer. Each stepped hole includes a first hole and a second hole under the first hole, a radius of the first hole at a bottom is a first radius, a radius of the second hole at a top is a second radius which is substantially smaller than the first radius, and a difference between the first radius and the second radius is 0.2 ?m to 0.6 ?m.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: July 26, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Leilei Cheng, Bin Zhou, Jun Liu, Luke Ding, Qinghe Wang, Yongchao Huang
  • Patent number: 11367792
    Abstract: The present disclosure is related to a thin film transistor. The thin film transistor may include an active layer; a gate insulating layer on the active layer; and a gate and a plurality of metal films on the gate insulating layer. The plurality of metal films may be spaced apart from the gate, and insulated from the gate and the active layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: June 21, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Song, Liangchen Yan, Ce Zhao, Heekyu Kim, Yuankui Ding, Leilei Cheng, Yingbin Hu, Wei Li, Guangyao Li, Qinghe Wang
  • Patent number: 11329115
    Abstract: The present disclosure relates to a pixel structure. The pixel structure may include a base substrate; a first insulating island on a side of the base substrate; a first electrode on a side of the first insulating island opposite front the base substrate; a second electrode on the base substrate and at a peripheral area of the first insulating island; an active layer electrically connected to the first electrode and the second electrode; a second insulating layer on a side of the active layer opposite from the base substrate; a gate electrode on a side of the second insulating layer opposite from the base substrate; and a third insulating layer on a side of the gate electrode opposite from the base substrate.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 10, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Song, Liangchen Yan, Ce Zhao, Heekyu Kim, Yuankui Ding, Leilei Cheng, Yingbin Hu, Wei Li, Yang Zhang
  • Publication number: 20220123095
    Abstract: The present disclosure provides an OLED display substrate, a manufacturing method thereof, and a display device, which relates to the field of display technologies. The OLED display substrate includes a light-shielding layer, a buffer layer, an active layer pattern, a gate insulating layer, a gate layer pattern, an interlayer insulating layer, a source-drain layer pattern, an anode, a light-emitting layer, and a cathode which are arranged in turn on a base substrate, wherein the source-drain layer pattern and/or the gate layer pattern are made of a transparent conductive material.
    Type: Application
    Filed: February 3, 2021
    Publication date: April 21, 2022
    Inventor: Leilei CHENG
  • Publication number: 20220115493
    Abstract: A display panel and a fabricating method thereof, and a displaying device. The display panel includes a substrate, a resistance reducing trace, an inter-layer-medium layer and a signal line. The substrate is divided into a plurality of sub-pixel regions and a pixel separating region. The resistance reducing trace is provided on the pixel separating region of the substrate. The inter-layer-medium layer is provided on the substrate, and the inter-layer-medium layer has an opening exposing the resistance reducing trace. The signal line is provided within the opening, the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.
    Type: Application
    Filed: May 25, 2021
    Publication date: April 14, 2022
    Applicants: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yongchao Huang, Can Yuan, Liusong Ni, Chao Wang, Jiawen Song, Zhiwen Luo, Jun Liu, Leilei Cheng, Qinghe Wang, Tao Sun
  • Patent number: 11287333
    Abstract: A pressure sensing unit includes: a first substrate and a second substrate opposite to each other; and at least one vertical thin film transistor disposed between the first substrate and the second substrate. Each vertical thin film transistor includes a first electrode, a semiconductor active layer, a second electrode, at least one insulating support, and a gate electrode sequentially disposed in a direction extending from the first substrate to the second substrate. A first air gap is formed by the presence of the at least one insulating support between the gate electrode and the second electrode of each vertical thin film transistor.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 29, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Qinghe Wang, Dongfang Wang, Bin Zhou, Ce Zhao, Tongshang Su, Leilei Cheng, Yang Zhang, Guangyao Li