Abstract: A method is provided for forming a Deep Neural Network (DNN). The method includes quantizing deep learning data structures of the DNN into at least two modes using at least two scale factors, respectively. Each of the at least two modes corresponds to a respective one of the at least two scale factors. The method further includes identifying which of the at least two scale factors to use for a given one of the data structures based on a data distribution of the given one of the data structures. The quantizing step includes identifying when a tail of the given one of the data structures starts by (i) building a histogram of values in the given one of the data structures using successive bins; (ii) identifying a ratio of density between the successive bins; and (iii) checking whether the ratio of density is greater than a ratio of density threshold.

Abstract: Voltage on the output terminal of an inductor is obtained as a first input signal to a control block (CB); the inductor has an input terminal connected to a power switch and driver block at a switching node. A sense input voltage is obtained on an output terminal of a sensing circuit that is not directly connected to the switching node, as a second input signal to the CB. A voltage is generated on a first output terminal of the CB and is selected such that the CB can use its first and second input signals to infer the current through the inductor. A pulse width modulation (PWM) signal is generated on a second output terminal of the CB, based on the inferred current through the inductor; the second output signal from the CB is provided to a PWM input terminal of the power switch and driver block.

Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Abstract: A multi-phase buck switching converter having grouped pairs of phases, each phase using two magnetically coupled air-core inductors. For each group, a first driver circuit controlling switching of a first power transistor switching circuit coupled to a first air-core inductor output for driving an output load at the first phase. A second driver circuit controlling switching of a second power transistor switching circuit coupled to a second air-core inductor output for driving said output load at the second phase. The first and second phases are spaced 180° apart. The coupled air-core inductors per group of such orientation, separation distance and mutual inductance polarity relative to each other such that magnetic coupling between the two or more inductors at each phase results in a net increase in effective inductance per unit volume. Each air-core inductor is a metal slab of defined length, height and thickness formed using back-end-of-line semiconductor manufacturing process.

Abstract: Technical solutions are described to accelerate training of a multi-layer convolutional neural network. According to one aspect, a computer implemented method is described. A convolutional layer includes input maps, convolutional kernels, and output maps. The method includes a forward pass, a backward pass, and an update pass that each include convolution calculations. The described method performs the convolutional operations involved in the forward, the backward, and the update passes based on a first, a second, and a third perforation map respectively. The perforation maps are stochastically generated, and distinct from each other. The method further includes interpolating results of the selective convolution operations to obtain remaining results. The method includes iteratively repeating the forward pass, the backward pass, and the update pass until the convolutional neural network is trained. Other aspects such as a system, apparatus, and computer program product are also described.

Abstract: A compensated deep neural network (compensated-DNN) is provided. A first vector having a set of components and a second vector having a set of corresponding components are received. A component of the first vector includes a first quantized value and a first compensation instruction, and a corresponding component of the second vector includes a second quantized value and a second compensation instruction. The first quantized value is multiplied with the second quantized value to compute a raw product value. The raw product value is compensated for a quantization error according to the first and second compensation instructions to produce a compensated product value. The compensated product value is added into an accumulated value for the dot product. The accumulated value is converted into an output vector of the dot product. The output vector includes an output quantized value and an output compensation instruction.

Abstract: A multi-phase buck switching converter having grouped pairs of phases, each phase using two magnetically coupled air-core inductors. For each group, a first driver circuit controlling switching of a first power transistor switching circuit coupled to a first air-core inductor output for driving an output load at the first phase. A second driver circuit controlling switching of a second power transistor switching circuit coupled to a second air-core inductor output for driving said output load at the second phase. The first and second phases are spaced 180° apart. The coupled air-core inductors per group of such orientation, separation distance and mutual inductance polarity relative to each other such that magnetic coupling between the two or more inductors at each phase results in a net increase in effective inductance per unit volume. Each air-core inductor is a metal slab of defined length, height and thickness formed using back-end-of-line semiconductor manufacturing process.

Abstract: Technical solutions are described to accelerate training of a multi-layer convolutional neural network. According to one aspect, a computer implemented method is described. A convolutional layer includes input maps, convolutional kernels, and output maps. The method includes a forward pass, a backward pass, and an update pass that each include convolution calculations. The described method performs the convolutional operations involved in the forward, the backward, and the update passes based on a first, a second, and a third perforation map respectively. The perforation maps are stochastically generated, and distinct from each other. The method further includes interpolating results of the selective convolution operations to obtain remaining results. The method includes iteratively repeating the forward pass, the backward pass, and the update pass until the convolutional neural network is trained. Other aspects such as a system, apparatus, and computer program product are also described.

Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.

Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.

Abstract: An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.

Abstract: An apparatus for storing data includes a latch circuit comprising a first set of transistors that propagate an input signal to an output signal and a second set of transistors that do not propagate the input signal of the latch circuit to the output signal wherein a gate pitch for the first set of transistors is substantially greater than a gate pitch for the second set of transistors. Also disclosed herein, a method for improving circuit performance includes receiving an electronic representation of a plurality of latching circuits associated with a design file and increasing transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal to an output signal. The method may also include fabricating a chip comprising the plurality of latching circuits. A computer program product corresponding to the method is also disclosed within.

Abstract: A semiconductor wafer is provided, where the semiconductor wafer includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. Fins are formed in the semiconductor substrate and the hard mask layer. A spacer is formed on an exposed sidewall of the hard mask layer and the semiconductor substrate. The exposed portion of the semiconductor substrate is etched. A silicon-germanium layer is epitaxially formed on the exposed portions of the semiconductor substrate. An annealed silicon-germanium region is formed by a thermal annealing process within the semiconductor substrate adjacent to the silicon-germanium layer. The silicon-germanium region and the silicon-germanium layer are removed. The hard mask layer and the spacer are removed.

Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.

Abstract: An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.