Abstract: A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic dilute mask is employed to implant a dopant into the target deep well region to form a deep well region with the selected region having a lowered dopant concentration. The lowered dopant concentration can yield a higher breakdown voltage for the bipolar device. The intrinsic dilute mask mitigates implantation within the selected region.

Abstract: According to one embodiment of the invention, a method of packaging ball grid arrays includes providing a substrate having a plurality of holes formed therein. Each hole is associated with a respective one of a plurality of contact pads formed on a first surface of the substrate. The method further includes disposing a plurality of balls within respective ones of the plurality of holes such that at least a portion of each ball projects outwardly from the first surface, and applying a force to each of the balls from above the first surface to couple the balls to the substrate.

Abstract: Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (130). Contacts are formed to the conductive layer (80) by etching openings in the carbon containing dielectric layer (140) and the optional dielectric layer (130).

Abstract: A semiconductor device comprising a metallic leadframe (103) with a first surface (103a) and a second surface (103b). The leadframe includes a chip pad (104) and a plurality of segments (107); the chip pad is held by a plurality of straps (105), wherein each strap has a groove (106). A chip (101) is mounted on the chip pad and electrically connected to the segments. A heat spreader (110) is disposed on the first surface of the leadframe; the heat spreader has its central portion (110a) spaced above the chip connections (108), and also has positioning members (110b) extending outwardly from the edges of the central portion so that they rest in the grooves of the straps. Encapsulation material surrounds the chip, the electrical connections, and the spreader positioning members, and fills the space between the spreader and the chip, while leaving the second leadframe surface and the central spreader portion exposed.

Abstract: Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbide layer provides an etch stop for etching the overlying oxide layer, and the underlying oxide layer provides an etch stop for etching the carbide layer to form an emitter-base contact opening.

Abstract: We disclose the structure of an electronic device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has, near the top surface, a buried layer that is electrically communicable to a drain terminal. The device has a body region over the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: In a method to singulate a semiconductor wafer (100) into chips, trench streets (107) of predetermined depth (105a) are formed across the first, active wafer surface (102) to define the outline of the chips (101). Thereafter, the fabrication of the active first wafer surface is completed and protected. Then, the wafer is flipped to expose the second wafer surface (103), and the wafer is subjected to a cutting saw. The saw is aligned with the trenches in the first surface so that the saw cuts the second surface along streets (106), which extend the trenches through the wafer. The saw is stopped cutting at a depth (105b), when the saw streets just coalesce with the trench streets, respectively, whereby the chips are completely singulated.

Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a body region above the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: One aspect of the invention is a semiconductor circuit comprising a semiconductor die electrically connected to a package substrate through a plurality of electrical contacts. A lid above and substantially parallel to the top surface of the die forms a portion of the semiconductor circuit package. A plurality of lid supports each comprising a post and standoff member collectively create a separation between the lid and top surface of the die.

Abstract: Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (130). Contacts are formed to the conductive layer (80) by etching openings in the carbon containing dielectric layer (140) and the optional dielectric layer (130).

Abstract: In one embodiment, solder balls of multiple sizes may be used to couple one or more semiconductor structures to an electrical device. For example, a printed circuit board structure may support one or more integrated circuit packages includes at least one package with a substrate having a bottom surface. The structure may also include a printed circuit board that includes: (1) one or more first regions each having a top surface opposite the bottom surface of the substrate and separated from the bottom surface by a first distance; and (2) one or more second regions each having a top surface opposite the bottom surface of the substrate and separated from the bottom surface of the substrate by a second distance, the top surface of the second region being closer to the bottom surface of the substrate than the top surface of the first region such that the second distance is smaller than the first distance.

Abstract: In a method to singulate a semiconductor wafer (100) into chips, trench streets (107) of predetermined depth (105a) are formed across the first, active wafer surface (102) to define the outline of the chips (101). Thereafter, the fabrication of the active first wafer surface is completed and protected. Then, the wafer is flipped to expose the second wafer surface (103), and the wafer is subjected to a cutting saw. The saw is aligned with the trenches in the first surface so that the saw cuts the second surface along streets (106), which extend the trenches through the wafer. The saw is stopped cutting at a depth (105b), when the saw streets just coalesce with the trench streets, respectively, whereby the chips are completely singulated.

Abstract: In a method to singulate a semiconductor wafer (100) into chips, trench streets (107) of predetermined depth (105a) are formed across the first, active wafer surface (102) to define the outline of the chips (101). Thereafter, the fabrication of the active first wafer surface is completed and protected. Then, the wafer is flipped to expose the second wafer surface (103), and the wafer is subjected to a cutting saw. The saw is aligned with the trenches in the first surface so that the saw cuts the second surface along streets (106), which extend the trenches through the wafer. The saw is stopped cutting at a depth (105b), when the saw streets just coalesce with the trench streets, respectively, whereby the chips are completely singulated.

Abstract: An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging-semiconductor devices, and within the passivating film layers, including the following sequence of materials deposited by PECVD processing: a thin film of silicon dioxide, a layer of silicon nitride, oxy-nitride or silicon carbide, and a very thin topmost layer of silicon oxide.

Abstract: A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88) of a microeffusion cell (86). The method then provides for transporting the substrate (40) across the port (88) at a substantially constant rate. The method then provides for effusing an emissive material from the port (88) and adhering at least a portion of the emissive material effused from the port (88) to a defined region of the substrate (40) to form an emissive strip (46) having a substantially constant width on the substrate (40).

Abstract: Laser alignment structures are formed over an integrated circuit by forming structures of a first width (90) adjacent to structures of a second width (100) where the second width is greater than five times the first width. In addition the structures of a first width are separated from each other by a distance that between one and five times the first width.

Abstract: Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (130). Contacts are formed to the conductive layer (80) by etching openings in the carbon containing dielectric layer (140) and the optional dielectric layer (130).

Abstract: A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88) of a microeffusion cell (86). The method then provides for transporting the substrate (40) across the port (88) at a substantially constant rate. The method then provides for effusing an emissive material from the port (88) and adhering at least a portion of the emissive material effused from the port (88) to a defined region of the substrate (40) to form an emissive strip (46) having a substantially constant width on the substrate (40).

Abstract: A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88) of a microeffusion cell (86). The method then provides for transporting the substrate (40) across the port (88) at a substantially constant rate. The method then provides for effusing an emissive material from the port (88) and adhering at least a portion of the emissive material effused from the port (88) to a defined region of the substrate (40) to form an emissive strip (46) having a substantially constant width on the substrate (40).

Abstract: A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88) of a microeffusion cell (86). The method then provides for transporting the substrate (40) across the port (88) at a substantially constant rate. The method then provides for effusing an emissive material from the port (88) and adhering at least a portion of the emissive material effused from the port (88) to a defined region of the substrate (40) to form an emissive strip (46) having a substantially constant width on the substrate (40).