Patents by Inventor Leonard Forbes

Leonard Forbes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140169103
    Abstract: Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type; biasing the second conductive region to a second voltage to forward bias the junction from the second conductive region to the first conductive region; and injecting electrons into a charge-storage node of the selected memory cell from the second conductive region. The first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 19, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Badih EL-KAREH, Leonard FORBES
  • Publication number: 20140167186
    Abstract: The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Arup Bhattacharyya, Leonard Forbes, Paul A. Farrar
  • Patent number: 8741746
    Abstract: A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8742515
    Abstract: The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. The dielectric structure can include hafnium oxide on a substrate surface followed by dysprosium oxide, and repeating to form a thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8734583
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20140138795
    Abstract: Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes, Arup Bhattacharyya
  • Patent number: 8685815
    Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8686489
    Abstract: The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the floating gate and a read wordline. A tunneling metal-insulator-metal capacitor is created between the floating gate and a write/erase bit line. In one embodiment, the insulator is a metal oxide.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20140084355
    Abstract: Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment, a monolayer or partial monolayer sequence process, such as for example atomic layer deposition (ALD), can be used to form a dielectric containing gadolinium oxide and scandium oxide. In an embodiment, a dielectric structure can be formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric containing scandium and gadolinium may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, as a NROM dielectric, or as a dielectric in other electronic devices, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film.
    Type: Application
    Filed: December 6, 2013
    Publication date: March 27, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8680591
    Abstract: Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: March 25, 2014
    Assignee: Sionyx, Inc.
    Inventors: Homayoon Haddad, Jutao Jiang, Jeffrey McKee, Drake Miller, Leonard Forbes, Chintamani Palsule
  • Patent number: 8679928
    Abstract: The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Arup Bhattacharyya, Leonard Forbes, Paul A. Farrar
  • Publication number: 20140065806
    Abstract: Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium strontium titanium oxide film using atomic layer deposition. Embodiments include forming erbium-doped barium strontium titanium oxide film using atomic layer deposition.
    Type: Application
    Filed: November 8, 2013
    Publication date: March 6, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8654592
    Abstract: Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric isolation structures contain an upper well having a first conductivity type and a buried well having a second conductivity type. By forward biasing the junction from the buried well to the upper well, electrons can be injected into charge-storage nodes of memory cells that are contained within the dielectric isolation structures.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Badih El-Kareh, Leonard Forbes
  • Patent number: 8652957
    Abstract: A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20140035101
    Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.
    Type: Application
    Filed: October 11, 2013
    Publication date: February 6, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Publication number: 20140038401
    Abstract: A gate containing ruthenium for a dielectric having an oxide containing a lanthanide and a method of fabricating such a combination gate and dielectric produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide gate may be formed on a lanthanide oxide. A ruthenium-based gate on a lanthanide oxide provides a gate structure that can effectively prevent a reaction between the gate and the lanthanide oxide.
    Type: Application
    Filed: October 11, 2013
    Publication date: February 6, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8637377
    Abstract: Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes, Arup Bhattacharyya
  • Patent number: 8637362
    Abstract: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8628615
    Abstract: An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and systems. The film of transparent conductive titanium-doped indium oxide may be structured as one or more monolayers. The film of transparent conductive titanium-doped indium oxide may be formed using atomic layer deposition.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8609523
    Abstract: A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes