Patents by Inventor Leonardus Antonius Elisabeth van Gemert

Leonardus Antonius Elisabeth van Gemert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10177111
    Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 8, 2019
    Assignee: NXP B.V.
    Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
  • Patent number: 10096555
    Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 9, 2018
    Assignee: NXP B.V.
    Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
  • Patent number: 9953903
    Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: April 24, 2018
    Assignee: NXP B.V.
    Inventors: Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis, Rintje van der Meulen, Emil Casey Israel
  • Publication number: 20170213797
    Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.
    Type: Application
    Filed: March 20, 2017
    Publication date: July 27, 2017
    Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
  • Patent number: 9704823
    Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 11, 2017
    Assignee: NXP B.V.
    Inventors: Tonny Kamphuis, Roelf Anco Jacob Groenhuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
  • Publication number: 20170179076
    Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 22, 2017
    Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
  • Patent number: 9653414
    Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: May 16, 2017
    Assignee: NXP B. V.
    Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
  • Publication number: 20170103939
    Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device. The method comprises providing a lead frame, the lead frame having I/O terminals surrounding a die attach region, the lead frame defined onto a temporary carrier. A device die is attached onto the die-attach region. The device die is wire bonded to the I/O terminals, the I/O terminals located in a first position. In a molding compound the wire-bonded device die and lead frame are encapsulated. The temporary carrier is removed from the lead frame, underside surfaces of the device die and I/O terminals are exposed. Applying a non-conductive layer to the exposed underside surfaces of the device die and I/O terminals, thereby defines features in which conductive traces may be defined from the I/O terminals in the first position to customized I/O terminals located in a second position.
    Type: Application
    Filed: October 9, 2015
    Publication date: April 13, 2017
    Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis
  • Publication number: 20170025369
    Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.
    Type: Application
    Filed: July 22, 2015
    Publication date: January 26, 2017
    Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
  • Publication number: 20170025334
    Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.
    Type: Application
    Filed: July 22, 2015
    Publication date: January 26, 2017
    Inventors: Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis, Rintje van der Meulen, Emil Casey Israel
  • Patent number: 9466585
    Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: October 11, 2016
    Assignee: NXP B.V.
    Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Franciscus Henrikus Martinus Swartjes, Jetse de Witte
  • Publication number: 20160276176
    Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.
    Type: Application
    Filed: October 29, 2015
    Publication date: September 22, 2016
    Inventors: Tonny Kamphuis, Roelf Anco Jacob Groenhuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
  • Publication number: 20160276306
    Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.
    Type: Application
    Filed: October 29, 2015
    Publication date: September 22, 2016
    Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Franciscus Henrikus Martinus Swartjes, Jetse de Witte
  • Patent number: 9385099
    Abstract: One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 5, 2016
    Assignee: NXP, B.V.
    Inventors: Leonardus Antonius Elisabeth van Gemert, Coenraad Cornelis Tak, Marten Oldsen, Hendrik Bouman
  • Patent number: 9263299
    Abstract: In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: February 16, 2016
    Assignee: NXP B.V.
    Inventors: Leonardus Antonius Elisabeth van Gemert, Emil Casey Israel
  • Patent number: 9245804
    Abstract: Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (?) of tooling impact upon a vertical face the semiconductor device.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: January 26, 2016
    Assignee: NXP B.V.
    Inventors: Christian Zenz, Hartmut Buenning, Leonardus Antonius Elisabeth Van Gemert, Tonny Kamphuis, Sascha Moeller
  • Publication number: 20160005653
    Abstract: Consistent with an example embodiment, there is a method for manufacturing integrated circuit (IC) devices from a wafer substrate, the wafer substrate having a front-side surface with active devices and a back-side surface. A temporary covering to the front-side of the wafer substrate is applied. The back-side of the wafer substrate having a pre-grind thickness is ground to a post-grind thickness. To a predetermined thickness, the back-side of the wafer substrate is coated with a resilient coating. The wafer is mounted onto a second carrier tape on its back-side surface. After removing the temporary carrier tape from the front-side of the wafer substrate, the wafer is sawed along active device boundaries and active devices are singulated.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Inventors: Caroline Catharina Maria Beelen-Hendrikx, Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert
  • Publication number: 20160005626
    Abstract: In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Inventors: Leonardus Antonius Elisabeth van Gemert, Emil Casey Israel
  • Publication number: 20160005680
    Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a heat sink array having a top-side surface and an under-side surface; the heat sink array has die placement areas on the top-side surface. A plurality of active device die are die bonded onto the die placement areas on the heat sink array. The plurality of active device die are singulated into an individual heat sink device die having a heat sink portion attached to its underside.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Inventors: Emil Casey Israel, Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis
  • Publication number: 20160005679
    Abstract: Consistent with an example embodiment, there is a method for packaging an integrated circuit (IC) device. The method comprises attaching a lead frame to the carrier tape; the lead frame has an array of device positions on the carrier tape and pad landings surround the device positions for making electrical connections to the plurality of active device die. A plurality of active device die are mounted on the carrier tape within the array of device positions; each said active device die has bond pads, each of said active device die has been subjected to back-grinding to a prescribed thickness and has a solderable conductive surface on its underside. On the bond pads, the plurality of active devices are wire bonded to the pad landings on the lead frame. The lead frame and wire bonded active devices are encapsulated, leaving the solderable die backside and lead frame backside exposed.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Inventors: Emil Casey Israel, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis