Patents by Inventor Leonel R. Arana

Leonel R. Arana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190304912
    Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Applicant: INTEL CORPORATION
    Inventors: Jeremy D. Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh, Leonel R. Arana, Chung Kwang Tan, Robert A. May
  • Patent number: 10078204
    Abstract: Embodiments include devices, systems and processes for using a combined confocal Raman microscope for inspecting a photo resist film material layer formed on the top surface of a layer of a substrate package, to detect border defects between regions of light exposed (e.g., cured) and unexposed (e.g., uncured) resist film material. Use of the confocal Raman microscope may provide a 3D photo-resist chemical imaging and characterization technique based on combining (1) Raman spectroscopy to identify the borders between regions of light exposed and unexposed resist along XY planes, with (2) Confocal imaging to select a Z-height of the XY planes scanned. Such detection provides fast, high resolution, non-destructive in-line inspection, and improves technical development of polymerization profiles of the resist film material.
    Type: Grant
    Filed: March 29, 2014
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: Nilanjan Z. Ghosh, Kevin T. McCarthy, Zhiyong Wang, Deepak Goyal, Changhua Liu, Leonel R. Arana
  • Patent number: 9808875
    Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Deepak V. Kulkarni, Carl L. Deppisch, Leonel R. Arana, Gregory S. Constable, Sriram Srinivasan
  • Patent number: 9793233
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Rajasekaran Swaminathan, Leonel R. Arana, Yoshihiro Tomita, Yosuke Kanaoka
  • Publication number: 20170284943
    Abstract: A system for detecting a void in a photoresist layer can include: a detector, a processor, and a memory. The detector can be arranged to receive reflected light from a surface of a sample. The processor can be in electrical communication with the detector, The memory can store instructions that, when executed by the processor, can cause the processor to perform operations. The operations can comprise: receiving optical data from the detector, receiving calibrated data, and determining an existence of the void. the optical data can include information regarding a signature of the reflected light. The calibrated data can include information regarding a signature for a known sample of photoresist. The determination of the existence of the void can be based on a deviation of the optical data from the calibrated data.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 5, 2017
    Inventors: Nilanjan Ghosh, Deepak Goyal, Jing Cheng, Leonel R. Arana
  • Patent number: 9659899
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Sandeep B. Sane, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Publication number: 20170032991
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 2, 2017
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Publication number: 20160343680
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Inventors: Rajasekaran SWAMINATHAN, Leonel R. ARANA, Yoshihiro TOMITA, Yosuke KANAOKA
  • Patent number: 9472519
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: October 18, 2016
    Assignee: INTEL CORPORATION
    Inventors: Rajasekaran Swaminathan, Leonel R. Arana, Yoshihiro Tomita, Yosuke Kanaoka
  • Publication number: 20160172222
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Publication number: 20160151850
    Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 2, 2016
    Inventors: Deepak V. Kulkarni, Carl L. Deppisch, Leonel R. Arana, Gregory S. Constable, Sriram Srinivasan
  • Patent number: 9254532
    Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Deepak V. Kulkarni, Carl L. Deppisch, Leonel R. Arana, Gregory S. Constable, Sriram Srinivasan
  • Publication number: 20150318258
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.
    Type: Application
    Filed: July 10, 2015
    Publication date: November 5, 2015
    Applicant: INTEL CORPORATION
    Inventors: SANDEEP B. SANE, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Publication number: 20150276480
    Abstract: Embodiments include devices, systems and processes for using a combined confocal Raman microscope for inspecting a photo resist film material layer formed on the top surface of a layer of a substrate package, to detect border defects between regions of light exposed (e.g., cured) and unexposed (e.g., uncured) resist film material. Use of the confocal Raman microscope may provide a 3D photo-resist chemical imaging and characterization technique based on combining (1) Raman spectroscopy to identify the borders between regions of light exposed and unexposed resist along XY planes, with (2) Confocal imaging to select a Z-height of the XY planes scanned. Such detection provides fast, high resolution, non-destructive in-line inspection, and improves technical development of polymerization profiles of the resist film material.
    Type: Application
    Filed: March 29, 2014
    Publication date: October 1, 2015
    Inventors: Nilanjan GHOSH, Kevin T. MCCARTHY, Zhiyong WANG, Deepak GOYAL, Changhua LIU, Leonel R. ARANA
  • Patent number: 9123732
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Sandeep B. Sane, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Publication number: 20150194401
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Application
    Filed: March 13, 2015
    Publication date: July 9, 2015
    Inventors: Rajasekaran SWAMINATHAN, Leonel R. ARANA, Yoshihiro TOMITA, Yosuke KANAOKA
  • Publication number: 20150187622
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2013
    Publication date: July 2, 2015
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Publication number: 20140091470
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Sandeep B. Sane, Shandar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Patent number: 8674519
    Abstract: A microelectronic package includes a substrate (110, 210), an interposer (120, 220) having a first surface (121) and an opposing second surface (122), a microelectronic die (130, 230) attached to the substrate, and a mold compound (140) over the substrate. The interposer is electrically connected to the substrate using a wirebond (150). The first surface of the interposer is physically connected to the substrate with an adhesive (160), and the second surface has an electrically conductive contact (126) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 18, 2014
    Assignee: Intel Corporation
    Inventors: Leonel R. Arana, Edward R. Prack, Robert M. Nickerson
  • Publication number: 20130292838
    Abstract: Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
    Type: Application
    Filed: July 10, 2013
    Publication date: November 7, 2013
    Inventors: Sanka Ganesan, Yosuke Kanaoka, Ram S. Viswanath, Rajasekaran Swaminathan, Robert M. Nickerson, Leonel R. Arana, John S. Guzek, Yoshihiro Tomita