Patents by Inventor Leonel R. Arana

Leonel R. Arana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8569108
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 29, 2013
    Assignee: Intel Corporation
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Patent number: 8513792
    Abstract: Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Yosuke Kanaoka, Ram S. Viswanath, Rajasekaran Swaminathan, Robert M. Nickerson, Leonel R. Arana, John S. Guzek, Yoshihiro Tomita
  • Publication number: 20130017650
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 17, 2013
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Patent number: 8287996
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Publication number: 20120153504
    Abstract: A microelectronic package includes a substrate (110, 210), an interposer (120, 220) having a first surface (121) and an opposing second surface (122), a microelectronic die (130, 230) attached to the substrate, and a mold compound (140) over the substrate. The interposer is electrically connected to the substrate using a wirebond (150). The first surface of the interposer is physically connected to the substrate with an adhesive (160), and the second surface has an electrically conductive contact (126) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Inventors: Leonel R. Arana, Edward R. Prack, Robert M. Nickerson
  • Publication number: 20110278719
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate and a die, and coupling the die to the substrate, wherein a gap remains between the die and the substrate. The method also includes placing an underfill material on the substrate and delivering at least part of the underfill material into the gap. The method also includes controlling the flow of the underfill material in the gap using magnetic force. Other embodiments are described and claimed.
    Type: Application
    Filed: July 18, 2011
    Publication date: November 17, 2011
    Inventors: Stephen E. LEHMAN, JR., Rahul N. MANEPALLI, Leonel R. ARANA, Wendy CHAN
  • Patent number: 8009442
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate and a die, and coupling the die to the substrate, wherein a gap remains between the die and the substrate. The method also includes placing an underfill material on the substrate and delivering at least part of the underfill material into the gap. The method also includes controlling the flow of the underfill material in the gap using magnetic force. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: August 30, 2011
    Assignee: Intel Corporation
    Inventors: Stephen E. Lehman, Jr., Rahul N. Manepalli, Leonel R. Arana, Wendy Chan
  • Publication number: 20110159310
    Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Deepak V. Kulkarni, Carl L. Deppisch, Leonel R. Arana, Gregory S. Constable, Sriram Srinivasan
  • Publication number: 20110156283
    Abstract: A microelectronic package comprises a die (110) having a front side (111) containing active circuitry (115) and a back side (112) opposite the front side and a film (120) on the back side of the die. The film has a thickness (121) of at least 20 micrometers, a Young's modulus of at least 10 GPa, and a post-cure glass transition temperature of at least 100° Celsius.
    Type: Application
    Filed: December 28, 2009
    Publication date: June 30, 2011
    Inventors: Shankar Ganapathysubramanian, Leonel R. Arana, Robert L. Sankman, Wen Janet Feng, Robert M. Nickerson
  • Publication number: 20110151624
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Patent number: 7592697
    Abstract: A microelectronic package comprises a chip stack (110) that includes a substrate (111), a first die (112) over the substrate and a second die (113) over the first die, a first underfill layer (114) between the substrate and the first die, and a second underfill layer (115) between the first die and the second die. The microelectronic package further comprises a fluidic microchannel system (120) in the chip stack, and the fluidic microchannel system comprises a fluid inlet (121) and a fluid outlet (122) connected to each other by a fluidic passage (123).
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: September 22, 2009
    Assignee: Intel Corporation
    Inventors: Leonel R. Arana, Michael W. Newman, Je-Young Chang
  • Publication number: 20090168390
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate and a die, and coupling the die to the substrate, wherein a gap remains between the die and the substrate. The method also includes placing an underfill material on the substrate and delivering at least part of the underfill material into the gap. The method also includes controlling the flow of the underfill material in the gap using magnetic force. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Inventors: Stephen E. LEHMAN, JR., Rahul N. MANEPALLI, Leonel R. ARANA, Wendy CHAN
  • Publication number: 20090057881
    Abstract: A microelectronic package comprises a chip stack (110) that includes a substrate (111), a first die (112) over the substrate and a second die (113) over the first die, a first underfill layer (114) between the substrate and the first die, and a second underfill layer (115) between the first die and the second die. The microelectronic package further comprises a fluidic microchannel system (120) in the chip stack, and the fluidic microchannel system comprises a fluid inlet (121) and a fluid outlet (122) connected to each other by a fluidic passage (123).
    Type: Application
    Filed: August 27, 2007
    Publication date: March 5, 2009
    Inventors: Leonel R. Arana, Michael W. Newman, Je-Young Chang
  • Publication number: 20090004317
    Abstract: A molding compound for use in an integrated circuit package comprises an epoxy and a thermally conductive filler material. The thermally conductive filler material comprises between 70% and 95% of the molding compound and has a thermal conductivity between 10 W/m-K and 3000 W/m-K.
    Type: Application
    Filed: June 30, 2007
    Publication date: January 1, 2009
    Inventors: Xuejiao Hu, Leonel R. Arana, Robert M. Nickerson, Rahul N. Manepalli, Dingying Xu
  • Patent number: 7462551
    Abstract: In some embodiments, an adhesive system for supporting thin silicon wafer is presented. In this regard, a method is introduced to bond a silicon wafer to a translucent carrier through the use of an adhesive. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: December 9, 2008
    Assignee: Intel Corporation
    Inventors: Sudhakar N. Kulkarni, Leonel R. Arana, Edward R. Prack
  • Publication number: 20080251932
    Abstract: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 16, 2008
    Inventors: Leonel R. Arana, Devendra Natekar, Michael Newman, Charan K. Gurumurthy
  • Publication number: 20080237843
    Abstract: A microelectronic package. The package includes a substrate; a die mounted onto the substrate; an integrated heat spreader mounted onto the substrate, and thermally coupled to a backside of the die; and a sealant material bonding the integrated heat spreader to the substrate, the sealant material having a bulk thermal conductivity above about 1 W/m/° C. and a modulus of elasticity lower than a modulus of elasticity of solder.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 2, 2008
    Inventors: Ashish Gupta, Leonel R. Arana, David Song, Chia-Pin Chiu, Ravi Prasher, Chris Matayabas, Nirupama Chakrapani
  • Publication number: 20080237841
    Abstract: A microelectronic package includes a substrate (110) having a first die (120) and a second die (130) located thereon, a first thermal interface material (121) located over the first die, and a second thermal interface material (131) located over the second die. The first thermal interface material has a first set of characteristics, the second thermal interface material has a second set of characteristics, and the first set of characteristics is not identical to the second set of characteristics.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 2, 2008
    Inventors: Leonel R. Arana, Vijay S. Wakharkar, James C. Matayabas, Paul A. Koning, Cynthia K. Koning
  • Patent number: 7402515
    Abstract: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: Leonel R. Arana, Devendra Natekar, Michael Newman, Charan K. Gurumurthy
  • Publication number: 20080171249
    Abstract: A micromachined device for efficient thermal processing at least one fluid stream includes at least one fluid conducting tube having at least a region with wall thickness of less than 50 ?m. The device optionally includes one or more thermally conductive structures in thermal communication with first and second thermally insulating portions of the fluid conducting tube. The device also may include a thermally conductive region, and at least a portion of the fluid conducting tube is disposed within the region. A plurality of structures may be provided projecting from a wall of the fluid conducting tube into an inner volume of the tube. The structures enhance thermal conduction between a fluid within the tube and a wall of the tube. A method for fabricating, from a substrate, a micromachined device for processing a fluid stream allows the selective removal of portions of the substrate to provide desired structures integrated within the device.
    Type: Application
    Filed: August 7, 2007
    Publication date: July 17, 2008
    Inventors: Leonel R. Arana, Aleksander J. Franz, Klavs F. Jensen, Samuel B. Schaevitz, Martin A. Schmidt