Abstract: A power saving device and method for either adding or subtracting a constant from an operand, by checking a logic value of a portion of the operand and deciding whether to activate a multi-bit adder or to perform the subtraction or addition by inverting a portion of the operand. The power saving device and method is especially efficient when the constant K equals 2n. Then, the n'th bit of the operand is checked and if the addition or subtraction operation can be performed by inverting the n'th bit of the operand, a result is generated by that inversion, while a multi-bit adder is disabled.

Abstract: A phase detector and a method for detecting phase difference between two high frequency signals, the phase detector is adapted to receive a reference signal REF, a high frequency signal ICOS, and a signal FD synchronized to ICOS. REF, ICOS and FD have opposite edges. The phase detector comprising of: An asynchronous phase detector circuit, for providing an asynchronous control signal CTP, for representing a time interval between a time of occurrence of an edge of REF and the time of occurrence of a corresponding edge of ICOS. A synchronous phase detector circuit, for providing an synchronous control signal TC, for representing a time interval between a time of the occurrence of the corresponding edge of ICOS and the time of occurrence of a corresponding edge of FD.A combing circuit, for receiving TC and CTP and providing an error signal ERS, representing the phase difference between REF and FD.