Patents by Inventor Li-Chieh Wu

Li-Chieh Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10957587
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Kuo-Hsiu Wei, Kei-Wei Chen, Tang-Kuei Chang, Chia Hsuan Lee, Jian-Ci Lin
  • Publication number: 20210082688
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.
    Type: Application
    Filed: November 10, 2020
    Publication date: March 18, 2021
    Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
  • Patent number: 10937691
    Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen
  • Patent number: 10928741
    Abstract: A method for a lithography exposure process is provided. The method includes irradiating a target droplet with a laser beam to create an extreme ultraviolet (EUV) light. The method further includes reflecting the EUV light with a collector. The method also includes discharging a cleaning gas over the collector through a gas distributor positioned next to the collector. A portion of the cleaning gas is converted to free radicals before the cleaning gas leaves the gas distributor, and the free radicals are discharged over the collector along with the cleaning gas.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Ying Wu, Shang-Chieh Chien, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
  • Patent number: 10916473
    Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
  • Patent number: 10875060
    Abstract: Debris is removed from a collector of an extreme ultraviolet light source vessel by applying a suction force through a vacuum opening of a cable. The method for removing debris also includes weakening debris attachment by using a sticky surface or by spreading a solution through a nozzle, wherein the sticky surface and the nozzle are arranged on the cable proximal to the vacuum opening. A borescope system and interchangeable rigid portions of the cable assists in targeting a target area of the collector where the debris is.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Ying Wu, Ming-Hsun Tsai, Sheng-Kang Yu, Yung-Teng Yu, Chi Yang, Shang-Chieh Chien, Chia-Chen Chen, Li-Jui Chen, Po-Chung Cheng
  • Patent number: 10847359
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
  • Publication number: 20200348241
    Abstract: A single-shot metrology for direct inspection of an entirety of the interior of an EUV vessel is provided. An EUV vessel including an inspection tool integrated with the EUV vessel is provided. During an inspection process, the inspection tool is moved into a primary focus region of the EUV vessel. While the inspection tool is disposed at the primary focus region and while providing a substantially uniform and constant light level to an interior of the EUV vessel by way of an illuminator, a panoramic image of an interior of the EUV vessel is captured by way of a single-shot of the inspection tool. Thereafter, a level of tin contamination on a plurality of components of the EUV vessel is quantified based on the panoramic image of the interior of the EUV vessel. The quantified level of contamination is compared to a KPI, and an OCAP may be implemented.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Chun-Lin Louis CHANG, Shang-Chieh CHIEN, Shang-Ying WU, Li-Kai CHENG, Tzung-Chi FU, Bo-Tsun LIU, Li-Jui CHEN, Po-Chung CHENG, Anthony YEN, Chia-Chen CHEN
  • Publication number: 20200350317
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Publication number: 20200331038
    Abstract: Debris is removed from a collector of an extreme ultraviolet light source vessel by applying a suction force through a vacuum opening of a cable. The method for removing debris also includes weakening debris attachment by using a sticky surface or by spreading a solution through a nozzle, wherein the sticky surface and the nozzle are arranged on the cable proximal to the vacuum opening. A borescope system and interchangeable rigid portions of the cable assists in targeting a target area of the collector where the debris is.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Ying WU, Ming-Hsun TSAI, Sheng-Kang YU, Yung-Teng YU, Chi YANG, Shang-Chieh CHIEN, Chia-Chen CHEN, Li-Jui CHEN, Po-Chung CHENG
  • Publication number: 20200278617
    Abstract: A method for a lithography exposure process is provided. The method includes irradiating a target droplet with a laser beam to create an extreme ultraviolet (EUV) light. The method further includes reflecting the EUV light with a collector. The method also includes discharging a cleaning gas over the collector through a gas distributor positioned next to the collector. A portion of the cleaning gas is converted to free radicals before the cleaning gas leaves the gas distributor, and the free radicals are discharged over the collector along with the cleaning gas.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Ying WU, Shang-Chieh CHIEN, Bo-Tsun LIU, Li-Jui CHEN, Po-Chung CHENG
  • Patent number: 10763260
    Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
  • Patent number: 10756090
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 25, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 10755934
    Abstract: A chemical mechanical polishing (CMP) system and associated semiconductor fabrication methods are disclosed herein. An exemplary method includes performing a planarization process in a polishing unit of a CMP system to planarize a surface of a material layer using a CMP slurry. The method further includes, after performing the planarization process, performing a buffing process in the polishing unit of the CMP system to buff the surface of the material layer using an ozone gas dissolved in deionized water (O3/DIW) solution. The method further includes controlling the performing of the planarization process and the performing of the buffing process, such that the CMP slurry is received by the polishing unit from a first pipeline during the planarization process and the O3/DIW solution is received by the polishing unit from a second pipeline during the buffing process.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shich-Chang Suen, Chi-Jen Liu, Ying-Liang Chuang, Li-Chieh Wu, Liang-Guang Chen, Ming-Liang Yen
  • Patent number: 10718718
    Abstract: A single-shot metrology for direct inspection of an entirety of the interior of an EUV vessel is provided. An EUV vessel including an inspection tool integrated with the EUV vessel is provided. During an inspection process, the inspection tool is moved into a primary focus region of the EUV vessel. While the inspection tool is disposed at the primary focus region and while providing a substantially uniform and constant light level to an interior of the EUV vessel by way of an illuminator, a panoramic image of an interior of the EUV vessel is captured by way of a single-shot of the inspection tool. Thereafter, a level of tin contamination on a plurality of components of the EUV vessel is quantified based on the panoramic image of the interior of the EUV vessel. The quantified level of contamination is compared to a KPI, and an OCAP may be implemented.
    Type: Grant
    Filed: September 29, 2019
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Lin Louis Chang, Shang-Chieh Chien, Shang-Ying Wu, Li-Kai Cheng, Tzung-Chi Fu, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng, Anthony Yen, Chia-Chen Chen
  • Patent number: 10672864
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Patent number: 10656539
    Abstract: A method for a lithography exposure process is provided. The method includes irradiating a target droplet with a laser beam to create an extreme ultraviolet (EUV) light. The method further includes reflecting the EUV light with a collector. The method also includes discharging a cleaning gas over the collector through a gas distributor positioned next to the collector. A portion of the cleaning gas is converted to free radicals before the cleaning gas leaves the gas distributor, and the free radicals are discharged over the collector along with the cleaning gas.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Ying Wu, Shang-Chieh Chien, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
  • Patent number: 10643892
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Publication number: 20200118823
    Abstract: A chemical mechanical polishing (CMP) system and associated semiconductor fabrication methods are disclosed herein. An exemplary method includes performing a planarization process in a polishing unit of a CMP system to planarize a surface of a material layer using a CMP slurry. The method further includes, after performing the planarization process, performing a buffing process in the polishing unit of the CMP system to buff the surface of the material layer using an ozone gas dissolved in deionized water (O3/DIW) solution. The method further includes controlling the performing of the planarization process and the performing of the buffing process, such that the CMP slurry is received by the polishing unit from a first pipeline during the planarization process and the O3/DIW solution is received by the polishing unit from a second pipeline during the buffing process.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Shich-Chang SUEN, Chi-Jen LIU, Ying-Liang CHUANG, Li-Chieh WU, Liang-Guang CHEN, Ming-Liang YEN
  • Publication number: 20200105580
    Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.
    Type: Application
    Filed: September 3, 2019
    Publication date: April 2, 2020
    Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen