Patents by Inventor Li-Chih Chen
Li-Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128324Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.Type: ApplicationFiled: November 21, 2022Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
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Patent number: 11956994Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.Type: GrantFiled: August 10, 2021Date of Patent: April 9, 2024Assignee: Applied Materials, Inc.Inventors: Chung-Chih Wu, Hoang Yan Lin, Guo-Dong Su, Zih-Rou Cyue, Li-Yu Yu, Wei-Kai Lee, Guan-Yu Chen, Chung-Chia Chen, Wan-Yu Lin, Gang Yu, Byung-Sung Kwak, Robert Jan Visser, Chi-Jui Chang
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Publication number: 20240074119Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.Type: ApplicationFiled: May 9, 2023Publication date: February 29, 2024Inventors: Ren-Chun CHANG, Wei-Chih LIN, Sheng-Chi WU, Wen-Yin TSAI, Li-Hsiu CHEN
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Patent number: 11915755Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.Type: GrantFiled: January 20, 2022Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
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Publication number: 20170191412Abstract: A hydrogen carbon cleaning method for a vehicle is provided, which includes the following steps. First, a reformer is provided. Then, high purity hydrogen is provided by the reformer. Next, a hydrogen carbon cleaning process is performed on a vehicle with the high purity hydrogen.Type: ApplicationFiled: June 17, 2016Publication date: July 6, 2017Inventors: Yu-Chou Tsai, Liam-Yung Sung, Jung-Kuei Chang, Li-Chih Chen, Jian-Kai Wang
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Patent number: 9205588Abstract: A hot runner nozzle structure includes a tubular nozzle and at least one temperature measurement component. The tubular nozzle has an outer wall surface and an inner wall surface defining a flow channel. The tubular nozzle has portions defining at least one thru-hole interconnected the outer wall surface and the inner wall surface. The temperature measurement component has a base and a sensor connected to the base. The base is fixed in the thru-hole. The sensor has a tip protruding beyond the inner wall surface and exposed in the flow channel.Type: GrantFiled: November 17, 2013Date of Patent: December 8, 2015Assignee: WISTRON CORP.Inventors: Yuan-Shiang Lin, An-Chen Hung, Li-Chih Chen, Chien-Yu Ko
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Publication number: 20140377395Abstract: A hot runner nozzle structure includes a tubular nozzle and at least one temperature measurement component. The tubular nozzle has an outer wall surface and an inner wall surface defining a flow channel. The tubular nozzle has portions defining at least one thru-hole interconnected the outer wall surface and the inner wall surface. The temperature measurement component has a base and a sensor connected to the base. The base is fixed in the thru-hole. The sensor has a tip protruding beyond the inner wall surface and exposed in the flow channel.Type: ApplicationFiled: November 17, 2013Publication date: December 25, 2014Applicant: WISTRON CORP.Inventors: YUAN-SHIANG LIN, AN-CHEN HUNG, LI-CHIH CHEN, CHIEN-YU KO
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Patent number: 8497584Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.Type: GrantFiled: March 26, 2004Date of Patent: July 30, 2013Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yen-Ming Chen, Chia-Fu Lin, Shun-Liang Hsu, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
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Patent number: 7906425Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: GrantFiled: October 13, 2006Date of Patent: March 15, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
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Patent number: 7276454Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.Type: GrantFiled: November 2, 2002Date of Patent: October 2, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Ming Ching, Chia Fu Lin, Wen-Hsiang Tseng, Ta-Min Lin, Yen-Ming Chen, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
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Publication number: 20070028445Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: ApplicationFiled: October 13, 2006Publication date: February 8, 2007Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
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Patent number: 7134199Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: GrantFiled: June 13, 2002Date of Patent: November 14, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
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Patent number: 6974659Abstract: A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.Type: GrantFiled: January 16, 2002Date of Patent: December 13, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen
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Patent number: 6802250Abstract: A stencil design for solder paste printing, or other metal stencil printing, is disclosed. A stencil for stencil printing of solder onto a semiconductor wafer for semiconductor wafer bumping includes a substrate. The substrate has a hole defined therein substantially shaped to correspond to and receptive to the semiconductor wafer. An interior edge of the substrate surrounds the hole, and has an upper lip under which the semiconductor wafer is positioned. The upper lip of the interior edge of the substrate surrounding the hole substantially prevents the solder from flowing onto sides and a bottom of the semiconductor wafer during stencil printing of the solder. The cross-profile shape of the upper lip may in one embodiment be rectangular, whereas in another embodiment be triangular.Type: GrantFiled: May 20, 2002Date of Patent: October 12, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen
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Publication number: 20040180296Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.Type: ApplicationFiled: March 26, 2004Publication date: September 16, 2004Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Yen-Ming Chen, Chia-Fu Lin, Shun-Liang Hsu, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
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Patent number: 6756294Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the Created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.Type: GrantFiled: January 30, 2002Date of Patent: June 29, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yen-Ming Chen, Chia-Fu Lin, Shun-Liang Hsu, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
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Patent number: 6743660Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the act of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. An electrically conductive redistribution trace is deposited over the under bump metallurgy. A photoresist layer is deposited, patterned and developed to provide portions selectively protecting the electrically conductive redistribution trace and the under bump metallurgy. Excess portions of the electrically conductive redistribution trace and under bump metallurgy not protected by the photoresist are removed.Type: GrantFiled: January 12, 2002Date of Patent: June 1, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Hsin-Hui Lee, Chia-Fu Lin, Chao-Yuan Su, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen
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Publication number: 20040000580Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4, SF4, and H2 and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: ApplicationFiled: June 27, 2002Publication date: January 1, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Hui Lee, Chia-Fu Lin, Chao-Yuan Su, Yeng-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Hao-Chih Tien
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Publication number: 20030229986Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: ApplicationFiled: June 13, 2002Publication date: December 18, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
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Publication number: 20030226638Abstract: A DFR laminating and PET removing system which is capable of both laminating a dry film resist (DFR) layer on a semiconductor wafer and removing a DFR support film such as polyethylene terepthalate (PET) from the DFR layer on the wafer at a single location. The DFR laminating and PET removing system of the present invention comprises a PET support film removing head for removing a portion of PET film from the semiconductor wafer substrate after the PET film portion and dry film resist (DFR) portion are laminated from a DFR tape onto the wafer and before the DFR portion is cut from the DFR tape.Type: ApplicationFiled: June 7, 2002Publication date: December 11, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Chih Chen, Chia-Tsun Hsu, Chia-Fu Lin, Kuo-Ching Lee, Yen-Ming Chen, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su