Abstract: A semiconductor device includes a semiconductor substrate, a body region of a first conductivity type in the substrate, a source region of a second conductivity type adjacent the body region, and a trench extending into the substrate. The trench contains a polysilicon gate electrode insulated from the substrate. The device further includes a dielectric layer on the substrate, a gate metallization on the dielectric layer and covering part of the substrate and a source metallization on the dielectric layer and electrically connected to the source region. The gate metallization includes two spaced apart fingers. The source metallization is spaced apart from the gate metallization and covers a different part of the substrate than the gate metallization. A metal-filled groove in the polysilicon gate electrode is electrically connected to the two spaced apart fingers, and extends along a length of the trench directly underneath at least part of the source metallization.

Abstract: In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.

Abstract: A semiconductor device includes needle-shaped field plate structures extending from a first surface into transistor sections of a semiconductor portion in a transistor cell area. A grid structure separates the transistor sections from each other. The grid structure includes: stripe-shaped gate edge portions extending along one edge of the transistor sections, respectively; gate node portions wider than the gate edge portions and connecting two or more of the gate edge portions, respectively; and one or more connection sections of the semiconductor portion, wherein the one or more connection sections extend between neighboring transistor sections.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.

Abstract: A method of manufacturing a power metal oxide semiconductor field effect transistor includes: forming a field electrode in a field plate trench in a main surface of a semiconductor substrate; forming a gate trench in the main surface, the gate trench extending in a first direction parallel to the main surface; and for a gate electrode in the gate trench, the gate electrode being made of a gate electrode material that comprises a metal. The field plate trench is formed to have an extension length in the first direction which is less than double of an extension length of the field plate trench in a second direction, the second direction being perpendicular to the first direction.

Abstract: A power MOSFET includes a gate electrode in a gate trench in a main surface of a semiconductor substrate, the gate trench extending parallel to the main surface. The power MOSFET further includes a field electrode in a field plate trench in the main surface. The field plate trench has an extension length in a first direction which is less than double and more than half of an extension length of the field plate trench in a second direction perpendicular to the first direction, the first and the second directions being parallel to the main surface. The gate electrode includes a gate electrode material which comprises a metal.

Abstract: In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.

Abstract: A semiconductor device includes a semiconductor body having a front side and a back side, and a trench included in the semiconductor body. The trench extends into the semiconductor body along an extension direction that points from the front side to the back side. The trench includes an electrode structure and an insulation structure, the insulation structure insulating the electrode structure from the semiconductor body and the electrode structure being arranged for receiving an electric signal from external of the semiconductor device. The electrode structure includes a first electrode and a second electrode in contact with the first electrode, the first electrode including a first electrode material and the second electrode including a second electrode material different from the first electrode material. The first electrode extends further along the extension direction as compared to the second electrode.

Abstract: There are disclosed herein various implementations of a vertical metal-oxide-semiconductor field-effect transistor (MOSFET). Such a vertical MOSFET includes a semiconductor substrate having a drift region situated over a drain, a gate trench and needle field plates extending into the drift region, and source regions situated in respective mesas. In addition, the vertical MOSFET includes mesa contacts having a first width and extending through a first pre-metal dielectric layer to make electrical contact with the mesas. A second pre-metal dielectric layer is situated over the first pre-metal dielectric layer and the mesa contacts. The vertical MOSFET further includes conductive posts having a second width less than the first width and extending through the second pre-metal dielectric layer to make electrical contact with the mesa contacts.

Abstract: A semiconductor device is produced by: creating an opening in a mask formed on a semiconductor body; creating, underneath the opening, a trench in the semiconductor body which has a side wall and a trench bottom; creating, while the mask is on the semiconductor body, an insulating layer covering the trench bottom and the side wall; depositing a spacer layer including a first electrode material on the insulating layer; removing the spacer layer from at least a portion of the insulating layer that covers the trench bottom; filling at least a portion of the trench with an insulating material; removing the part of the insulating material laterally confined by the spacer layer so as to leave an insulating block in the trench; and filling at least a portion of the trench with a second electrode material so as to form an electrode within the trench.

Abstract: A method of forming a semiconductor device is provided. The device includes a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.

Abstract: A semiconductor substrate has a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.

Abstract: A semiconductor device is produced by: creating an opening in a mask formed on a semiconductor body; creating, underneath the opening, a trench in the semiconductor body which has a side wall and a trench bottom; creating, while the mask is on the semiconductor body, an insulating layer covering the trench bottom and the side wall; depositing a spacer layer including a first electrode material on the insulating layer; removing the spacer layer from at least a portion of the insulating layer that covers the trench bottom; filling at least a portion of the trench with an insulating material; removing the part of the insulating material laterally confined by the spacer layer so as to leave an insulating block in the trench; and filling at least a portion of the trench with a second electrode material so as to form an electrode within the trench.

Abstract: A semiconductor substrate has a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.

Abstract: First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask.

Abstract: A semiconductor device includes a field electrode structure with a field electrode and a field dielectric surrounding the field electrode. A semiconductor body includes a transistor section surrounding the field electrode structure and including a source zone, a first drift zone section and a body zone separating the source zone and the first drift zone section. The body zone forms a first pn junction with the source zone and a second pn junction with the first drift zone section. A gate structure surrounds the field electrode structure and includes a gate electrode and a gate dielectric separating the gate electrode and the body zone. A contact structure directly adjoins the source and body zones and surrounds the field electrode structure equably with respect to the field electrode structure.

Abstract: A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.

Abstract: A power MOSFET includes a gate electrode in a gate trench in a main surface of a semiconductor substrate, the gate trench extending parallel to the main surface. The power MOSFET further includes a field electrode in a field plate trench in the main surface. The field plate trench has an extension length in a first direction which is less than double and more than half of an extension length of the field plate trench in a second direction perpendicular to the first direction, the first and the second directions being parallel to the main surface. The gate electrode includes a gate electrode material which comprises a metal.

Abstract: A semiconductor body has a first surface, a second opposing surface, an edge, an active device region, and an edge termination region. A trench extends from the first surface into the semiconductor body in the edge termination region and includes sidewalls and an insulated electrode. A first conductivity type doped region extends from the first surface into the semiconductor body in the edge termination region and has a planar outer surface along the first surface that adjoins the trench at a corner of the trench sidewall and the first surface and has a side surface extending from the corner along the trench sidewall. A first interconnect contacts the trench electrode. A second interconnect contacts the outer surface and the side surface. A contact couples the first doped region to the trench electrode and has a bottom surface coplanar with the first surface from a contact edge to the corner.

Abstract: A semiconductor device includes a semiconductor substrate, a body region of a first conductivity type in the substrate, a source region of a second conductivity type adjacent the body region, and a trench extending into the substrate. The trench contains a polysilicon gate electrode insulated from the substrate. The device further includes a dielectric layer on the substrate, a gate metallization on the dielectric layer and covering part of the substrate and a source metallization on the dielectric layer and electrically connected to the source region. The gate metallization includes two spaced apart fingers. The source metallization is spaced apart from the gate metallization and covers a different part of the substrate than the gate metallization. A metal-filled groove in the polysilicon gate electrode is electrically connected to the two spaced apart fingers, and extends along a length of the trench directly underneath at least part of the source metallization.