Patents by Inventor Li-Ming Chang

Li-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210057530
    Abstract: A semiconductor device includes a substrate, a source/drain structure, a source/drain contact, a gate structure, a first etching stop layer, and a via contact. The source/drain structure is over the substrate. The source/drain contact is over the source/drain contact. The gate structure is over the substrate. The first etching stop layer is over the gate structure, in which the first etching stop layer includes a first portion and a second portion, and a thickness of the first portion is lower than a thickness the second portion. The via contact extends along a top surface of the first portion of the first etching stop layer to a sidewall of the second portion of the first etching stop layer.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen YU, Chia-Hao CHANG, Cheng-Chi CHUANG, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20210049976
    Abstract: A projector and a projection method are provided. The projector is coupled to a display card and includes a light source, a light valve, a projection lens, and a processor. The light source provides an illumination beam. The light valve converts the illumination beam into an image beam. The projection lens projects the image beam to the outside of the projector to form an imaged image. The processor receives an input image signal from the display card, and generates a control signal corresponding to the input image signal according to a refresh rate of the input image signal. When the refresh rate is greater than a threshold, the imaged image has a first resolution. When the refresh rate is less than the threshold, the light valve performs a pixel shifting operation, so that the imaged image has a second resolution. The first resolution is less than the second resolution.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 18, 2021
    Applicant: Coretronic Corporation
    Inventors: Hsin-Yueh Chang, Li-Ming Chen
  • Patent number: 10910520
    Abstract: An optoelectronic device includes a semiconductor stack; a current blocking region, including a first pad portion formed on the semiconductor stack and wherein the current blocking region includes insulated material; a first opening, formed in the first pad portion, exposing a top surface of the semiconductor stack; a transparent conductive layer, formed on the current blocking region and/or the top surface of the semiconductor stack, including a second opening exposing the first opening; and a first electrode, formed on the transparent conductive layer and including a first pad electrode formed on the first pad portion of the current blocking region and electrically connecting to the semiconductor stack through the first opening; wherein in a top view, the first opening and the second opening have different shapes.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: February 2, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Tzung-Shiun Yeh, Li-Ming Chang, Chien-Fu Shen
  • Publication number: 20210020817
    Abstract: A light-emitting device includes: a substrate, including a first edge, a second edge, a third edge and a fourth edge; a semiconductor stack formed on the substrate, comprising a first semiconductor layer, a second semiconductor layer and an active layer; a first electrode formed on the first semiconductor layer, comprising a first pad electrode; and a second electrode formed on the second semiconductor layer, comprising a second pad electrode and a second finger electrode; wherein in a top view, the first pad electrode is adjacent to a corner of the substrate that is intersected by the first and the second edges; the second finger electrode is not parallel with the third and the first edges; and a distance between the second finger electrode and the first edge increases along a direction from an end of the second finger electrode that connects the second pad electrode toward the second edge.
    Type: Application
    Filed: August 5, 2020
    Publication date: January 21, 2021
    Inventors: Li-Ming CHANG, Tzung-Shiun YEH, Chien-Fu SHEN, Yu-Rui LIN, Chen OU, Hsin-Ying WANG, Hui-Chun YEH
  • Publication number: 20210014162
    Abstract: A router including a communication device, a first processor, and a second processor. The communication device is configured to receive a plurality of first packets of a connection and at least one second packet of the connection subsequent to the first packets The first processor, coupled to the communication device, and configured to analyze the first packets to determine at least part of a plurality of transport-layer parameters associated with the connection, receive a traffic control rule associated with the connection, and offload processing of the at least one second packet of the connection to a second processor after the at least part of the transport-layer parameters is determined. The second processor is configured to perform traffic control on the second packet according to the traffic control rule and the at least part of the transport-layer parameters.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Li-Fong HSU, Kuang-Ming LI, Cheng-Pang CHANG
  • Patent number: 10872406
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 10868000
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The method includes forming a dielectric layer over the first epitaxial structure, the second epitaxial structure, and the semiconductor substrate. The method includes forming a first mask layer over the dielectric layer and between the first epitaxial structure and the second epitaxial structure. The method includes forming a second mask layer over the dielectric layer and the first mask layer. The method includes partially removing the dielectric layer covering the first epitaxial structure and the second epitaxial structure. The method includes removing the first mask layer. The method includes forming a first conductive layer and a second conductive layer respectively in the first recess and the second recess.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Tien-Lu Lin, Jia-Chuan You, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 10819632
    Abstract: A router including a communication device, a first controller, a storage device, and a second controller is provided. The communication device receives a plurality of first packets of a connection and at least one second packet of the connection subsequent to the first packets. The first controller analyzes the first packets to determine a plurality of transport-layer parameters associated with the connection. The storage device stores the transport-layer parameters. The second controller performs traffic management on the second packet according to at least part of the transport-layer parameters stored in the storage device.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: October 27, 2020
    Assignee: SYNOLOGY INC.
    Inventors: Li-Fong Hsu, Kuang-Ming Li, Cheng-Pang Chang
  • Publication number: 20200303590
    Abstract: An optoelectronic device includes a semiconductor stack; a current blocking region, including a first pad portion formed above the semiconductor stack and wherein the current blocking region includes insulated material; a first opening, formed in the first pad portion, exposing a top surface of the semiconductor stack; a transparent conductive layer, formed on the current blocking region and/or the top surface of the semiconductor stack, including a second opening exposing the first opening; and a first electrode, formed on the transparent conductive layer and including a first pad electrode formed above the first pad portion of the current blocking region and electrically connecting to the semiconductor stack through the first opening; wherein in a top view, the first opening and the second opening have different shapes.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 24, 2020
    Inventors: Tzung-Shiun YEH, Li-Ming CHANG, Chien-Fu SHEN
  • Patent number: 10784427
    Abstract: A light-emitting device includes a first edge to a fourth edge; a semiconductor stack formed on a substrate, including a first semiconductor layer, a second semiconductor layer and an active layer; a first electrode formed on the first semiconductor layer, including a first pad electrode and a first finger electrode; and a second electrode formed on the second semiconductor layer, including a second pad electrode and a second finger electrode; wherein the first finger electrode is disposed at and along the first edge; and the first finger electrode includes a first overlapping portion overlapping the second finger electrode; the second finger electrode includes a second overlapping portion overlapping the first finger electrode and a non-overlapping portion that does not overlap the first finger electrode; and the second overlapping portion is not parallel with the first overlapping portion and the non-overlapping portion is not parallel with the first edge.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 22, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Li-Ming Chang, Tzung-Shiun Yeh, Chien-Fu Shen, Yu-Rui Lin, Chen Ou, Hsin-Ying Wang, Hui-Chun Yeh
  • Publication number: 20200243714
    Abstract: A light-emitting device, includes: a substrate, including a base with a main surface; and a plurality of protrusions on the main surface, wherein the protrusion and the base include different materials; and a semiconductor stack on the main surface, including a side wall, and wherein an included angle between the side wall and the main surface is an obtuse angle; wherein the main surface includes a peripheral area surrounding the semiconductor stack, and the peripheral area is devoid of the protrusion formed thereon.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 30, 2020
    Inventors: Li-Ming CHANG, Tzung-Shiun YEH, Chien-Fu SHEN, Wen-Hsiang LIN, Pei-Chi CHIANG, Yi-Wen KU
  • Publication number: 20200243519
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The method includes forming a dielectric layer over the first epitaxial structure, the second epitaxial structure, and the semiconductor substrate. The method includes forming a first mask layer over the dielectric layer and between the first epitaxial structure and the second epitaxial structure. The method includes forming a second mask layer over the dielectric layer and the first mask layer. The method includes partially removing the dielectric layer covering the first epitaxial structure and the second epitaxial structure. The method includes removing the first mask layer. The method includes forming a first conductive layer and a second conductive layer respectively in the first recess and the second recess.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Zhen YU, Tien-Lu LIN, Jia-Chuan YOU, Chia-Hao CHANG, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20200234617
    Abstract: A display apparatus and method for optimizing a display mode are provided. The display apparatus and method for optimizing a display mode include a display, a memory and a processor. The memory includes a sampling module, a neural network module and a mode selection module. The display displays an image data stream and has display modes. The sampling module samples the image data stream in a first time interval to generate sampling data in response to a trigger signal. The neural network module classifies the sampling data through the neural network to generate a classification outcome corresponding to the display modes. The mode selection module selects one of the display modes according to the classification outcome to display the image data stream.
    Type: Application
    Filed: January 14, 2020
    Publication date: July 23, 2020
    Applicants: Coretronic Corporation, Optoma Corporation
    Inventors: Hsin-Yueh Chang, Li-Ming Chen, Yuan-Mao Tsui
  • Patent number: 10707376
    Abstract: An optoelectronic device includes a substrate; a semiconductor stack, formed on the substrate; a current blocking region, including a first pad portion formed above the semiconductor stack and wherein the current blocking region includes transparent insulated material; a transparent conductive layer, formed on the current blocking region and/or a surface of the semiconductor stack; a first opening, formed in the first pad portion, wherein in a top view, the first opening includes elongated shape; and a first electrode, including a first pad electrode formed above the first pad portion of the current blocking region and electrically connecting to the semiconductor stack through the first opening.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: July 7, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Tzung-Shiun Yeh, Li-Ming Chang, Chien-Fu Shen
  • Patent number: 10673813
    Abstract: The present invention provides a method for NAT traversal in VPN so that the VPN can detect the rule of port allocation for NAT outside the VPN to achieve NAT traversal. The communication structure according to the present invention includes a public network, a client network, a destination network, a first NAT, a second NAT. A DNAT-T proxy server is installed between the first NAT and the second NAT and has the function for the VPN to conduct a plurality of (N times) registrations before sending data out to detect the rule for NAT port allocation of the DNAT-T proxy server, and then inform the next NAT port allocation to the other side of the VPN so as to achieve NAT traversal for the data packets in VPN.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 2, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hsueh Ming Hang, Shaw Hwa Hwang, Cheng Yu Yeh, Bing Chih Yao, Kuan Lin Chen, Yao Hsing Chung, Shun Chieh Chang, Chi Jung Huang, Li Te Shen, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh
  • Publication number: 20200134122
    Abstract: A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 30, 2020
    Inventors: Po-Hsiang HUANG, Sheng-Hsiung CHEN, Chih-Hsin KO, Fong-Yuan CHANG, Clement Hsingjen WANN, Li-Chun TIEN, Chia-Ming HSU
  • Patent number: 10633569
    Abstract: A composition and a solution for temporary bonding are provided. The composition includes a dianhydride monomer, a light-absorbing monomer, and a light-absorbing material. The light-absorbing monomer includes at least one of N,N,N,N-(p-aminophenyl)-p-phenylenediamine (TPDA) and N,N-(p-aminophenyl)-p-phenylenediamine (DPDA). The light-absorbing material includes carbon black and silicon dioxide.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIFLEX Scientific Co., Ltd.
    Inventors: Hsiu-Ming Chang, Tsung-Tai Hung, Li-Jung Hsiao, Po-Wen Lin
  • Publication number: 20200126865
    Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.
    Type: Application
    Filed: April 2, 2019
    Publication date: April 23, 2020
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20200105937
    Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.
    Type: Application
    Filed: July 17, 2019
    Publication date: April 2, 2020
    Inventors: Li-Zhen Yu, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20200052155
    Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-layers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N/GaN stack, where 0<x1?1 and 0?y1<1, and for the remainder of the potential barrier sub-layers, each of the potential barrier sub-layers is a GaN layer. An LED device including the multi-quantum well structure is also disclosed.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: HAN JIANG, YUNG-LING LAN, WEN-PIN HUANG, CHANGWEI SONG, LI-CHENG HUANG, FEILIN XUN, CHAN-CHAN LING, CHI-MING TSAI, CHIA-HUNG CHANG