Patents by Inventor Li-Ting Chen

Li-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384436
    Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220367664
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 17, 2022
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Publication number: 20220359511
    Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20220328631
    Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.
    Type: Application
    Filed: June 10, 2021
    Publication date: October 13, 2022
    Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
  • Publication number: 20220328266
    Abstract: A keyswitch assembly includes a switch module, a support mechanism, a blocking mechanism, an enhancing light source, and a backlight source. The switch module includes a substrate, a signal generator, and a signal sensor. The signal generator generates a sensing signal. The signal sensor receives the sensing signal to obtain a sensing strength. The support mechanism is disposed on the substrate. The blocking mechanism is disposed on the substrate and has a light-permeable portion. A portion of the blocking mechanism inserts into or escapes from a gap between the signal generator and the signal sensor. The backlight source is disposed on the substrate and located outside the vertical projection of the blocking mechanism on the substrate. The enhancing light source is disposed on the substrate and located within the vertical projection of the blocking mechanism on the substrate and corresponds to the light-permeable portion.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 13, 2022
    Inventors: Li-Te CHANG, Chih-Hung CHEN, Yen-Ting CHEN
  • Publication number: 20220328265
    Abstract: A keyswitch assembly includes a switch module, a support mechanism, and a blocking mechanism. The switch module includes a substrate, a signal generator, and a signal sensor. The signal generator provides a sensing signal. The signal sensor receives the sensing signal to obtain a sensing intensity. The support mechanism is disposed on the substrate. A top portion of the support mechanism moves in response to a pressing force. The blocking mechanism includes a pivoting portion rotatably disposed on the substrate, a connecting piece extending from the pivoting portion and movably connected to the support mechanism to be driven by the top portion to swivel relative to the substrate, and a blocking piece extending from the pivoting portion and driven by the connecting piece to be inserted into or escape from the gap between the signal generator and the signal sensor to change the magnitude of the sensing intensity.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 13, 2022
    Inventors: Li-Te CHANG, Chih-Hung CHEN, Yen-Ting CHEN
  • Publication number: 20220328420
    Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Patent number: 11444028
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 11437484
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Publication number: 20220278097
    Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220278067
    Abstract: A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua-Wei Tseng, Yueh-Ting Lin, Shao-Yun Chen, Li-Hsien Huang, An-Jhih Su, Ming-Shih Yeh, Der-Chyang Yeh
  • Patent number: 11430190
    Abstract: A virtual and real image fusion method is disclosed. The method comprises the following operations: obtaining a picture of a three dimensional space by a first camera, in which the picture comprises a screen picture and a tag picture of an entity tag and the screen picture is projected on the entity tag; obtaining a corresponding point data of the entity tag on the screen picture according to the picture by a processor; obtaining a spatial correction parameter according to the corresponding point data by the processor; and displaying an image on the screen picture according to the spatial correction parameter by the processor.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: August 30, 2022
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Li-Ting Chen, Ming-Fang Weng
  • Publication number: 20220238632
    Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Inventors: Kuo-Chih Lai, Chi-Mao Hsu, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Hsin-Fu Huang
  • Publication number: 20220238561
    Abstract: An electronic device of an embodiment of the disclosure includes a first substrate, a second substrate, and a driving layer. The first substrate and the second substrate are disposed opposite to each other, and the driving layer is disposed between the first substrate and the second substrate. The driving layer includes a scan line and a data line. The scan line is disposed on the first substrate and includes a first scan line segment. The first scan line segment has an opening and includes a first branch and a second branch. The first branch and the second branch are located on two opposite sides of the opening and are electrically connected in parallel with each other. The data line is disposed on the first substrate and intersects with the scan line. The electronic device of the embodiment of the disclosure may exhibit ideal display effect.
    Type: Application
    Filed: April 14, 2022
    Publication date: July 28, 2022
    Applicant: Innolux Corporation
    Inventors: Hung-Kun Chen, Li-Wei Sung, Shuo-Ting Hong, Chung-Le Chen
  • Patent number: 11393769
    Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Patent number: 11390677
    Abstract: The present invention provides antibodies that bind to CD47 with high affinity and specificity, and their use in treatment of a cancer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 19, 2022
    Assignee: TRICAN BIOTECHNOLOGY CO., LTD.
    Inventors: Huang-Tsu Chen, Jiun-Shyang Leou, Chung-Yuan Hsu, Cheng-Ke Li, Yun-Ting Wang, Li-Tsen Lin, Shiou-Ting Chen, Chen-Wei Chiang
  • Publication number: 20220181215
    Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20220114789
    Abstract: A virtual and real image fusion method is disclosed. The method comprises the following operations: obtaining a picture of a three dimensional space by a first camera, in which the picture comprises a screen picture and a tag picture of an entity tag and the screen picture is projected on the entity tag; obtaining a corresponding point data of the entity tag on the screen picture according to the picture by a processor; obtaining a spatial correction parameter according to the corresponding point data by the processor; and displaying an image on the screen picture according to the spatial correction parameter by the processor.
    Type: Application
    Filed: January 13, 2021
    Publication date: April 14, 2022
    Inventors: Li-Ting CHEN, Ming-Fang WENG
  • Patent number: 11264282
    Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20210359095
    Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.
    Type: Application
    Filed: April 2, 2021
    Publication date: November 18, 2021
    Inventors: Chi-Sheng Lai, Yu-Fan Peng, Li-Ting Chen, Yu-Shan Lu, Yu-Bey Wu, Wei-Chung Sun, Yuan-Ching Peng, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Pei-Yi Liu, Jing Yi Yan