Abstract: A double patterning method of manufacturing select gates and word lines is provided in the present invention, including forming first string patterns composed of word line patterns and select gate patterns on a target layer, forming a conformal spacer layer on first string patterns, wherein the spacer layer forms trenches between first string patterns, forming a fill layer filling up the trenches on the spacer layer, removing fill layer outside of the trenches, so that fill layer in the trenches forms second string patterns, wherein the second string patterns and the first string patterns are spaced apart, removing exposed spacer layer, so that the first string patterns and the second string patterns constitute target patterns spaced apart from each other on the target layer, and performing an etching process using those target patterns as a mask to remove exposed target layer, so as to form word lines and select gates.

Abstract: The invention provides a switch device including a shell, an operating member, a spring, a movable conductor, a first pin, a second pin, two resistors, and two connecting conductors. The operating member is partially exposed out of the shell, and the movable conductor is displaced when the operating member is operated. One side of the shell is provided with the first pin and the spring, another side is provided with the second pin. The resistors are connected with the second pin and have different resistance values. The connecting conductors are arranged between the two pins. The first pin contacts with the movable conductor. The connecting conductors without disposal of any crossover part therebetween and respectively connected with the resistors. The connecting conductors are arranged at intervals along a displacement path of the movable conductor which contacted one connecting conductor before and after displacement and forming two conductive paths.

Abstract: A new memory cell combination is disclosed. It includes a static random access memory (SRAM) unit and a mask read only memory (MROM) unit. The prior art separates the two memory units in different areas on a chip so that the circuit layout is not optimized. The disclosed cell combines them in the same area, saving more than 20% of the area.

Abstract: A new memory cell combination is disclosed. It includes a static random access memory (SRAM) unit and a mask read only memory (MROM) unit. The prior art separates the two memory units in different areas on a chip so that the circuit layout is not optimized. The disclosed cell combines them in the same area, saving more than 20% of the area.