Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.

Abstract: A dummy pattern arrangement and a method of arranging dummy patterns are provided in the present invention. The dummy pattern arrangement includes a substrate with a dummy region, a plurality of first base dummy cells arranged spaced apart from each other along a first direction in the dummy region, and two first edge dummy cells arranged respectively at two opposite sides of the first base dummy cells along the first direction in the dummy region.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

Abstract: The present invention provides a method for preparing a reconstituted apolipoprotein B lipoparticle and the method comprises steps of (a) dissolving an apolipoprotein B and a lipid in a first buffer containing 2 M to 8 M urea and 1 wt % to 15 wt % amphiphilic compounds to form a mixture; and (b) dialyzing the mixture against a second buffer containing 0 M to 2M urea and 0 wt % to 0.5 wt % amphiphilic compounds for 1 to several times for lowering concentrations of the urea and the amphiphilic compounds in the mixture. The present invention further provides an apolipoprotein B lipoparticle and a use for the production of an apolipoprotein B lipoparticle used for delivering a hydrophobic substance.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.

Abstract: A transistor includes an isolation region surrounding an active region. The transistor also includes a gate dielectric layer over a portion of the active region. The transistor further includes a gate electrode over the gate dielectric layer. The portion of the active region under the gate dielectric layer includes a channel region between a drain region and a source region, and at least one wing region adjoining the channel region. The at least one wing region has a base edge adjoining the channel region. The at least one wing region is polygonal or curved.

Abstract: A method for producing a silicon-containing zirconia calcined body includes wet mixing a mixture to obtain a mixed slurry, with the mixture including a silicon-containing zirconia powder, a sodium carbonate powder, a tetraethoxysilane, and an adhesive; drying the mixed slurry to obtain a caked mass; grinding and sieving the caked mass to obtain a mixed powder; pressurizing and shaping the mixed powder to obtain a blank; and calcining the blank in an environment at 900-1200° C. to obtain a silicon-containing zirconia calcined body. The silicon-containing zirconia calcined body can be sintered at 1415-1450° C. into a silicon-containing zirconia sintered body, with a shrinkage ratio during sintering the silicon-containing zirconia calcined body into the silicon-containing zirconia sintered body being 22-31%.

Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.

Abstract: A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area where low voltage devices are to be formed as well as gate structures of high voltage devices while performing high energy implants for the high voltage devices. Another method of semiconductor fabrication includes performing high energy implants for high voltage devices through a patterned photoresist where the photoresist is patterned prior to forming gate structures for high voltage devices and prior to forming gate structures for low voltage devices. After the high energy implants are performed, subsequent processing is performed to form high voltage devices and low voltage devices. High voltage device and low voltage devices are thus formed in a CMOS process without need for additional masks.

Abstract: The present invention provides a process for preparing a water dispersion containing a high concentration of nano/submicron, hydrophobic, functional compounds. The process is carried out by using a complex stabilizer having an HLB value of about 10 to about 17, comprising lecithin and at least one non-phospholipid selected from polysorbate, sucrose ester, and polyglycerol fatty acid ester; selecting a specific weight ratio of the hydrophobic functional compounds and the stabilizer; and using homogenization technique, media milling technique, and/or centrifugal technique. The water dispersion containing a high concentration of nano/submicron, hydrophobic, functional compound produced by the process of the invention has stable dispersibility and improved bioavailability, and can be applied to the fields of foods and pharmaceuticals.

Abstract: Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET.

Abstract: An integrated circuit and a method of forming is provided. The method includes forming a first well in a substrate, the first well having a first conductivity type, and forming a first source/drain region in the first well, the first source/drain region having a second conductivity type. A resistance protection ring is formed on the substrate.

Abstract: A method for producing a silicon-containing zirconia calcined body includes wet mixing a mixture to obtain a mixed slurry, with the mixture including a silicon-containing zirconia powder, a sodium carbonate powder, a tetraethoxysilane, and an adhesive; drying the mixed slurry to obtain a caked mass; grinding and sieving the caked mass to obtain a mixed powder; pressurizing and shaping the mixed powder to obtain a blank; and calcining the blank in an environment at 900-1200° C. to obtain a silicon-containing zirconia calcined body. The silicon-containing zirconia calcined body can be sintered at 1415-1450° C. into a silicon-containing zirconia sintered body, with a shrinkage ratio during sintering the silicon-containing zirconia calcined body into the silicon-containing zirconia sintered body being 22-31%.

Abstract: Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET.

Abstract: A wheel chair with urinal device includes a wheel chair a cushion connected thereto and the cushion has a hole. A drain pan with a slanted bottom wall is removably located beneath the cushion and a drain hole is defined through the lower front end of the slanted bottom wall. Multiple outlets defined in the support frame communicate with the space above the slanted bottom wall. A box is removably attached to the rear side of the backrest and has a collection unit and a cleaning unit received therein. The cleaning unit provides detergent to clean and flush the waste in the drain pan and collected in the collection unit. The user activates and controls the cleaning unit by operating a cleaning switch on the armrest.

Abstract: Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed.

Abstract: A divider for a bay of a blade server chassis includes a plurality of posts, a plurality of flex tabs, and a rail. The posts are located along a first side of the divider, and are configured to be inserted within respective holes in a first panel of the bay of the blade server chassis. The flex tabs are located along a second side of the divider, and are placed in physical communication with a second panel of the bay. The flex tabs are configured compress within the divider and away from the second panel to enable the posts to be inserted in the holes of the first panel, the second side of the divider being opposite to the first side of the divider. The rail is located along a third side of the divider, and is configured to guide a blade server within the bay.

Abstract: The present invention concerns combination of an amount of a BRS-3 agonist with an amount of a dipeptidyl peptidase IV (DPP-IV) inhibitor such that the combination provides an effect in lowering a blood glucose level or in increasing a blood GLP-1 level in a subject over that provided by the amount of the BRS-3 agonist alone and by the amount of the DPP-IV inhibitor alone and the use of such a combination for treating or preventing obesity and diabetes and conditions related thereto and conditions ameliorated by increasing a blood GLP-1 level. The present invention also relates to the use of a G protein-coupled receptor to screen for GLP-1 secretagogues.

Abstract: A transistor includes an isolation region surrounding an active region. The transistor also includes a gate dielectric layer over a portion of the active region. The transistor further includes a gate electrode over the gate dielectric layer. The portion of the active region under the gate dielectric layer includes a channel region between a drain region and a source region, and at least one wing region adjoining the channel region. The at least one wing region has a base edge adjoining the channel region. The at least one wing region is polygonal or curved.