Patents by Inventor Lih-Jyh Weng
Lih-Jyh Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7346834Abstract: A system that produces one or more non-repeating randomizer sequences of up to 2m?1 or more m-bit symbols includes a randomizer circuit that is set up in accordance with a polynomial with primitive elements of GF(2m) as coefficients. The system combines the randomizer sequence with all the symbols of ECC code words that are encoded using a BCH code over GF(2m) to produce a randomized code word. The particular primitive elements used and/or an initial state of one or more registers in the system specifies the particular sequence produced by the system. The initial state of each of the one or more registers is a selected one of the 2m?1 elements of GF(2m), and thus, 2m?1 different sequences may be produced by selecting a different initial state for a given one of the registers. If the coefficients are also selected from, for example, a set of “p” possible values, the system produces p*(2m?1) different sequences.Type: GrantFiled: June 20, 2005Date of Patent: March 18, 2008Assignee: Maxtor CorporationInventor: Lih-Jyh Weng
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Patent number: 7278085Abstract: A method of and apparatus for handling errors occurring in data stored in memory is presented. Data to be stored in a buffer memory is applied to a generator matrix to generate parity check bits. The parity check bits are stored in the buffer memory along with the data. The stored data and parity check bits are read and the read data is used to regenerate the parity check bits. A result produced from the stored and regenerated parity check bits is usable to directly identify a location of an erroneous bit of the data in the buffer memory.Type: GrantFiled: June 27, 2003Date of Patent: October 2, 2007Assignee: Maxtor CorporationInventors: Lih-Jyh Weng, Bruce Buch
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Patent number: 7181677Abstract: An encoding system manipulates L m-bit data symbols or sequences in accordance with a “restricted-symbol” code to produce code words that include error correction code (ECC) redundancy information and also meet modulation requirements, such as run length. The system combines the data and associated redundancy information of a code word D of the underlying code and one or more predetermined symbols or sequences that are appended to the data code word with the corresponding symbols or bit sequences of a selected code word F, to produce a transmission code word C that consists of symbols or sequences that meet the modulation requirements. Thereafter, the system corrects any errors in the retrieved or received code word C using the included redundancy information and the L m-bit data symbols or sequences are then recovered by removing therefrom the contributions of the code word F.Type: GrantFiled: June 19, 2003Date of Patent: February 20, 2007Assignee: Maxtor CorporationInventor: Lih-Jyh Weng
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Patent number: 7085988Abstract: A hashing system produces hash values by manipulating n-bit sequences in accordance with a selected distance d error correction code (“ECC”) over an associated Galois Field. The current system produces a hash value for a given n-bit sequence by treating the sequence as either a corrupted n-bit ECC codeword or as “n” information bits of an (n+r)-bit ECC codeword. The hashing system may decode the n bits as a corrupted codeword of an (n, k, d) perfect ECC to produce an n-bit error-free codeword, and then use as the hash value the information bits of the error-free codeword. Alternatively, the hashing system may treat the n-bit sequence as a corrupted code word of a cyclic distance d ECC, and map the codeword to an (n?k)-bit “error pattern” that the system then uses as the hash value. The hashing system may instead treat the n-bit sequence as n “information” bits and encode the bits in accordance with an (n+r, n, d) ECC, to produce an r-bit hash value that consists of the associated redundancy bits.Type: GrantFiled: March 20, 2003Date of Patent: August 1, 2006Assignee: Maxtor CorporationInventor: Lih-Jyh Weng
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Patent number: 6978415Abstract: A multiple-stage encoder encodes the data in accordance with one, two, . . . , or f factors of an associated cyclic code generator polynomial g(x)=g1(x)*g2(x)* . . . *gf(x) to produce data code words that include a selected number of ECC symbols. The encoder encodes the data d(x) in a first stage using a first factor gm(x) of a selected polynomial ps(x) to produce d(x)*xs=q1(x)g1(x)+r1(x), where q1(x) is a quotient and r1(x) is a remainder and g1(x) has degree s. In a next stage the encoder encodes q1(x) using a next factor gm(x) of the selected polynomial to produce qm(x)=q1(x)gm(x)+rm(x) and so forth, until the remainders associated with all of the factors of the selected generator polynomial have been produced. The system then manipulates the remainders to produce a remainder rs(x) that is associated with the selected polynomial ps(x), and uses a cyclically shifted version of the remainder rs(x) as the code word ECC symbols.Type: GrantFiled: November 27, 2001Date of Patent: December 20, 2005Assignee: Maxtor CorporationInventor: Lih-Jyh Weng
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Patent number: 6968493Abstract: A system that produces one or more non-repeating randomizer sequences of up to 2m?1 or more m-bit symbols includes a randomizer circuit that is set up in accordance with a polynomial with primitive elements of GF(2m) as coefficients. The system combines the randomizer sequence with all the symbols of ECC code words that are encoded using a BCH code over GF(2m) to produce a randomized code word. The particular primitive elements used and/or an initial state of one or more registers in the system specifies the particular sequence produced by the system. The initial state of each of the one or more registers is a selected one of the 2m?1 elements of GF(2m), and thus, 2m?1 different sequences may be produced by selecting a different initial state for a given one of the registers. If the coefficients are also selected from, for example, a set of “p” possible values, the system produces p*(2m?1) different sequences.Type: GrantFiled: September 14, 1999Date of Patent: November 22, 2005Assignee: Maxtor CorporationInventor: Lih-Jyh Weng
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Publication number: 20050229086Abstract: A system that produces one or more non-repeating randomizer sequences of up to 2m-1 or more m-bit symbols includes a randomizer circuit that is set up in accordance with a polynomial with primitive elements of GF(2m) as coefficients. The system combines the randomizer sequence with all the symbols of ECC code words that are encoded using a BCH code over GF(2m) to produce a randomized code word. The particular primitive elements used and/or an initial state of one or more registers in the system specifies the particular sequence produced by the system. The initial state of each of the one or more registers is a selected one of the 2m-1 elements of GF(2m), and thus, 2m-1 different sequences may be produced by selecting a different initial state for a given one of the registers. If the coefficients are also selected from, for example, a set of “p” possible values, the system produces p*(2m-1) different sequences.Type: ApplicationFiled: June 20, 2005Publication date: October 13, 2005Inventor: Lih-Jyh Weng
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Patent number: 6779011Abstract: A system determines the multiplicative inverse of A∈GF(22M) by representing A using a selected basis in which basis elements are squares of one another, and performing various operations that involve raising A to powers of 2 as cyclic rotations of A. The system also performs multiplication operations over GF(22M) or subfields thereof by calculating the coefficients of the product of two elements A and B that are represented using the selected basis as combinations of the coefficients of cyclically rotated versions of A and B. The system further utilizes a relatively small look-up table that contains the multiplicative inverses of selected elements of a subfield of GF(22M). The system may then cyclically rotate the multiplicative inverse values read from the table to produce the multiplicative inverses of the remaining elements of the subfield.Type: GrantFiled: February 28, 2001Date of Patent: August 17, 2004Assignee: Maxtor CorporationInventors: Lih-Jyh Weng, Dana Hall, Christine Imrich
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Patent number: 6772390Abstract: A method of determining error values including loading an error correction code (ECC) entity having rows representing data symbols, determining an error location for a first row, generating an error syndrome for the first row, determining an erasure constant array from the error location, determining an error location for each of the remaining rows, generating an error syndrome for each of the remaining rows and determining the error values for each of the rows from the corresponding error location and corresponding error syndrome and the constant.Type: GrantFiled: November 30, 2000Date of Patent: August 3, 2004Assignee: Quantum CorporationInventors: Lih-Jyh Weng, Dana Hall
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Patent number: 6769088Abstract: A mechanism for providing error protection for data that is to be stored in a data storage system in which data are stored in data sectors in a data storage area and redundant information that provides error protection for the data are stored in redundant sectors in a redundant storage area. New data that is written to a designated one of the data sectors, and that is not error protected by the redundant information, is received, and error correction information for the new data is selectively stored in an additional storage area to provide error protection for the new data instead of revising the redundant information to provide such error protection.Type: GrantFiled: June 30, 1999Date of Patent: July 27, 2004Assignee: Maxtor CorporationInventor: Lih-Jyh Weng
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Patent number: 6701336Abstract: Two types of shared-field multipliers for performing multiplications on field elements of different sizes are presented. One type uses a “cyclic” Galois field GF(2m), that is, a Galois field GF(2m) generated by an irreducible polynomial xm+xm−1+xm−2+ . . . +x+1, and the other type uses a composite field structure. Each shared-field multiplier includes computation circuitry for receiving field elements as inputs, the computation circuitry being responsive to a control signal to perform computations based on the inputs having a first size to produce an output of the first size, or to perform computations based on the inputs having a second, different size to produce an output of the second size.Type: GrantFiled: November 12, 1999Date of Patent: March 2, 2004Assignee: Maxtor CorporationInventors: Ba-Zhong Shen, Lih-Jyh Weng
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Patent number: 6651214Abstract: A bidirectional code decoding method and apparatus is presented. It uses a class of Reed-Solomon codes capable of bidirectional decoding, more specifically, those for which a value of L for a Galois Field element &agr;L is chosen as −(R−1)/2 for odd values of R and 2(m−1)−R/2 for even values of R. When the symbols of such codes are received at a decoder in a reverse order (from that in which the symbols are normally received) during a reverse directional read, the decoder produces reverse directional syndromes S˜(−k) and converts the reverse directional syndromes S˜(−k) to syndromes S(k) by multiplying S˜(−k) by &agr;(n−1)k for k=L, L+1, . . . , L+R−1.Type: GrantFiled: January 6, 2000Date of Patent: November 18, 2003Assignee: Maxtor CorporationInventors: Lih-Jyh Weng, Dana E. Hall
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Patent number: 6643819Abstract: A root finding mechanism uses an affine polynomial to find the roots of an error locator polynomial. The affine polynomial is produced from the error locator polynomial and field elements for generating roots of the affine polynomial are determined. Gray code is used to select the field elements used to generate the different roots of the affine polynomial. The roots are tested as possible true roots of the error locator polynomial.Type: GrantFiled: January 26, 2000Date of Patent: November 4, 2003Assignee: Maxtor CorporationInventor: Lih-Jyh Weng
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Patent number: 6640319Abstract: An R-stage error correction system constructed in accordance with a distance d Reed-Soloman code performs a modified encoding step to include in the encoding a predetermined non-zero “coset symbol” that results in the encoder producing a code word for recording that includes a coset leader of a distance d-1 code. During the modified encoding step, the coset symbol is included in the value produced by the Rthstage of the encoder during the encoding of a code word data symbol or a first redundancy symbol. The coset symbol is thereafter included in the encoding of the remaining redundancy symbols when the value produced by the last stage is fed back to the preceding stages. During decoding, the system decodes the code word and the included coset leader to generate associated error syndromes. In a last decoding step, the system removes the effects of the included coset leader from the syndromes, by combining a predetermined syndrome value with the syndrome value generated in the Rthstage .Type: GrantFiled: August 29, 2000Date of Patent: October 28, 2003Assignee: Maxtor CorporationInventor: Lih-Jyh Weng
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Patent number: 6637002Abstract: A decoder for decoding block error correction codes is described. The decoder includes a first search circuit to find roots of an error location polynomial corresponding to an error location and a second search circuit to find roots of an error location polynomial corresponding to an error location. A multiplexer is fed by the first search circuit and the second search circuit to produce an error location from the error location polynomial.Type: GrantFiled: October 21, 1998Date of Patent: October 21, 2003Assignee: Maxtor CorporationInventors: Lih-Jyh Weng, Ba-Zhong Shen, Shih Mo, Chung Chang
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Patent number: 6581180Abstract: A system for performing a Chien search simultaneously tests multiple elements of GF(2P) as possible roots of a degree-t error locator polynomial &sgr;(x) using a plurality of simplified multipliers that each simultaneously produce the corresponding terms of &sgr;(x). In one embodiment of the system, t−1 simplified multipliers over GF(2P) are used to simultaneously test as possible roots &agr;2, (&agr;2)2, (&agr;2)3 . . . (&agr;2)j. Each multiplier includes a plurality of adders that are set up in accordance with precomputed terms that are based on combinations of the weight-one elements of GF(2P). A summing circuit adds together the associated terms produced by the multipliers and produces j sums, which are then evaluated to test the j individual elements as possible roots. The coefficients of &sgr;(&agr;2)j are then fed back to the multipliers, and the multipliers test, during a next clock cycle, the elements &agr;2*(&agr;2)j, (&agr;2)2*(&agr;2)j . . . , (&agr;2)2j and so forth.Type: GrantFiled: March 17, 2000Date of Patent: June 17, 2003Assignee: Maxtor CorporationInventor: Lih-Jyh Weng
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Patent number: 6560747Abstract: A mechanism for determining a number of errors in an error correction code codeword is presented. The mechanism obtains the degree of an error locator polynomial associated with syndromes generated for the codeword without determining coefficients of the error locator polynomial. The degree is identified as the number of errors. The degree is determined from the syndromes using a Euclidean process which determines the degree without finding the coefficients. Alternatively, the degree is determined by forming a trapezoid-shaped matrix from the syndrome values and finding the rank of that matrix.Type: GrantFiled: November 10, 1999Date of Patent: May 6, 2003Assignee: Maxtor CorporationInventor: Lih-Jyh Weng
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Patent number: 6493845Abstract: A parallel input/output combined encoding and syndrome generating system encodes two information symbols per clock cycle, and thereafter, produces two redundancy symbols per clock cycle. For an n-symbol code word with 2k information symbols cn−1, to cn−2k, the symbols cn−1, cn−3, cn−5 . . . are supplied, in turn, to a first input line while the symbols cn−2, cn−4, cn−6, . . . are supplied, in turn, to a second input line. In a first clock cycle, the symbol cn−1 is combined with the contents of the R registers, where R is the number of redundancy symbols, and the contents are multiplied by the respective roots of the generator polynomial. The products then are combined with the paired symbol cn−2 and the resulting sums are multiplied also by the roots of the generator polynomial. These products are then summed in a chain of R adders and the respective registers are appropriately updated with the results of the encoding of the two symbols.Type: GrantFiled: June 21, 1999Date of Patent: December 10, 2002Assignee: Maxtor CorporationInventors: Ba-Zhong Shen, Lih-Jyh Weng, Diana L. Langer
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Publication number: 20020156823Abstract: A system determines the multiplicative inverse of A∈GF(22M) by representing A using a selected basis in which basis elements are squares of one another, and performing various operations that involve raising A to powers of 2 as cyclic rotations of A. The system also performs multiplication operations over GF(22M) or subfields thereof by calculating the coefficients of the product of two elements A and B that are represented using the selected basis as combinations of the coefficients of cyclically rotated versions of A and B. The system further utilizes a relatively small look-up table that contains the multiplicative inverses of selected elements of a subfield of GF(22M). The system may then cyclically rotate the multiplicative inverse values read from the table to produce the multiplicative inverses of the remaining elements of the subfield.Type: ApplicationFiled: February 28, 2001Publication date: October 24, 2002Inventors: Lih-Jyh Weng, Dana Hall, Christine Imrich
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Patent number: 6463564Abstract: An error correction system produces a code word for recording by XOR'ing to a data code word that is encoded in accordance with a distance d Reed-Solomon code a coset leader that is a code word of a distance d′ super code of the distance d code, but not a code word of the distance d code. When the code word is later retrieved, the system XOR's the coset leader to the retrieved code word. If there is no synchronization error, the XOR'ing operation reproduces the original data code word. If, however, there is a synchronization error, the XOR'ing operation introduces into the retrieved code word a term that is a Hamming distance of d′ from every valid code word of the distance d Reed-Solomon code. The result should then contain more errors than the ECC can correct, as long as d ′ > d 2 .Type: GrantFiled: September 14, 1999Date of Patent: October 8, 2002Assignee: Maxtor CorporationInventor: Lih-Jyh Weng