Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements (and/or circuit components) in a circuit design, by recording previously calculated markings and reusing the markings on subsequent marking iterations or processes. Marking information corresponding to each marking point includes indications of what types of interconnect elements or circuit components can be positioned at the marking point location without violating a design rule. With a dynamic caching process, once the marking computations have been completed for an element and the corresponding points in the vicinity, those values are stored in a cache. The next time the router encounters another instance of a known element-to-point relationship, the stored values are reloaded and applied to the current point.

Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements (and/or circuit components) in a circuit design, by recording previously calculated markings and reusing the markings on subsequent marking iterations or processes. Marking information corresponding to each marking point includes indications of what types of interconnect elements or circuit components can be positioned at the marking point location without violating a design rule. With a dynamic caching process, once the marking computations have been completed for an element and the corresponding points in the vicinity, those values are stored in a cache. The next time the router encounters another instance of a known element-to-point relationship, the stored values are reloaded and applied to the current point.

Abstract: A method for preparing an ?-Al2O3 nanotemplate of fully crystalline ?-Al2O3 directly on the surface of a metal alloy is provided. Also provided is a related apparatus.

Abstract: A method for preparing an ?-Al2O3 nanotemplate of fully crystalline ?-Al2O3 directly on the surface of a metal alloy is provided. Also provided is a related apparatus.

Abstract: An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: A method for preparing an &agr;-Al2O3 nanotemplate of fully crystalline &agr;-Al2O3 directly on the surface of a metal alloy is provided. Also provided is a related apparatus.

Abstract: Microencapsulated medicine of ox adrenal medulla pheochromocyte (BBC) for treating pain is prepared through the following steps: 1. suspending BBC in solution of sodium alginate; 2. dispersing the suspension in solution of calcium chloride to form calcium alginate bead deposit; 3. mixing the deposit with solution of polylysine to form a coating and depositing; 4. mixing the deposit with sodium alginate to form a coating; 5. displacing the calcium ions in deposit with sodium citrate for microencapsulating BBC; 6. transferring the microencapsulated BBC into culture liquid for storage. The medicine can release analgesic substance for several months after it be implanted into human body.

Abstract: A method for preparing an &agr;-Al2O3 nanotemplate of fully crystalline &agr;-Al2O3 directly on the surface of a metal alloy is provided. Also provided is a related apparatus.

Abstract: Microencapsulated medicine of ox adrenal medulla pheochromocyte (BBC) for treating pain is prepared through the following steps: 1. suspending BBC in solution of sodium alginate; 2. dispersing the suspension in solution of calcium chloride to form calcium alginate bead deposit; 3. mixing the deposit with solution of polylysine to form a coating and depositing; 4. mixing the deposit with sodium alginate to form a coating; 5. displacing the calcium ions in deposit with sodium citrate for microencapsulating BBC; 6. transferring the microencapsulated BBC into culture liquid for storage. The medicine can release analgesic substance for several months after it be implanted into human body.

Abstract: An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: An integrated circuit design is divided into partitions which each contain two stages of information. The first stage corresponds to sources within the design, and the second stage corresponds to targets within the design. In one implementation, all of the sources in each partition are triggered by a common clock edge. In another implementation, all targets of each partition are triggered by a common clock edge. Specifying timing constraints in partitions can provide an efficient method of determining how much slack, if any, is present in the timing of a design.