Patents by Inventor Lino A. Velo
Lino A. Velo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220142488Abstract: Automated systems and methods are presented for determining the physiological response of human or suitable animal subjects to physical exertion. The methods and systems can include monitoring sensors that capture the motion of the subject along with corresponding physiological data, and can track such motion for the duration of a period of physical exertion. The system is able to acquire an initial stream of physiological data from the subject during a range of physical exertion activities that are representative of the events intended to be monitored with the proposed method and system, enabling a corresponding dynamic physiological response model to be created. The motion tracking system and physiological response model can then be used to predict the physiological response to physical exertion events under a prescribed framework, including applications during real-time event monitoring.Type: ApplicationFiled: May 13, 2021Publication date: May 12, 2022Applicant: Salutron, Inc.Inventor: Lino Velo
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Publication number: 20220143462Abstract: Automated systems and methods are presented for determining the physiological response of human or suitable animal subjects to physical exertion. The methods and systems can include monitoring sensors that capture the motion of the subject along with corresponding physiological data, and can track such motion for the duration of a period of physical exertion. The system is able to acquire an initial stream of physiological data from the subject during a range of physical exertion activities that are representative of the events intended to be monitored with the proposed method and system, enabling a corresponding dynamic physiological response model to be created. The motion tracking system and physiological response model can then be used to predict the physiological response to physical exertion events under a prescribed framework, including applications during real-time event monitoring.Type: ApplicationFiled: May 13, 2021Publication date: May 12, 2022Applicant: Salutron, Inc.Inventor: Lino Velo
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Publication number: 20220142511Abstract: Automated systems and methods are presented for determining the physiological response of human or suitable animal subjects to physical exertion. The methods and systems can include monitoring sensors that capture the motion of the subject along with corresponding physiological data, and can track such motion for the duration of a period of physical exertion. The system is able to acquire an initial stream of physiological data from the subject during a range of physical exertion activities that are representative of the events intended to be monitored with the proposed method and system, enabling a corresponding dynamic physiological response model to be created. The motion tracking system and physiological response model can then be used to predict the physiological response to physical exertion events under a prescribed framework, including applications during real-time event monitoring.Type: ApplicationFiled: May 13, 2021Publication date: May 12, 2022Applicant: Salutron, Inc.Inventor: Lino Velo
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Patent number: 11291401Abstract: Described herein are user-wearable devices, and methods for use therewith, for monitoring for one or more types of arrhythmias based on a photoplethysmography (PPG) signal obtained using an optical sensor of a user-wearable device. A PPG based statistical and/or machine learning model is used to analyze a PPG signal, obtained using the optical sensor, to monitor for one or more types of arrhythmias including atrial fibrillation (AF). In response to detecting an arrhythmia based on the PPG signal, an electrocardiogram (ECG) signal is obtained using an ECG sensor of the user-wearable device. An ECG based statistical and/or machine learning model is used to analyze the ECG signal obtained using the ECG sensor of the user-wearable device to confirm or reject the arrhythmia detected based on the PPG signal and/or to perform arrhythmia discrimination. Obtained PPG and/or ECG signal segments can be provided to the model(s) to update the model(s).Type: GrantFiled: September 28, 2018Date of Patent: April 5, 2022Assignee: Salutron, Inc.Inventor: Lino Velo
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Publication number: 20200100693Abstract: Described herein are user-wearable devices, and methods for use therewith, for monitoring for one or more types of arrhythmias based on a photoplethysmography (PPG) signal obtained using an optical sensor of a user-wearable device. A PPG based statistical and/or machine learning model is used to analyze a PPG signal, obtained using the optical sensor, to monitor for one or more types of arrhythmias including atrial fibrillation (AF). In response to detecting an arrhythmia based on the PPG signal, an electrocardiogram (ECG) signal is obtained using an ECG sensor of the user-wearable device. An ECG based statistical and/or machine learning model is used to analyze the ECG signal obtained using the ECG sensor of the user-wearable device to confirm or reject the arrhythmia detected based on the PPG signal and/or to perform arrhythmia discrimination. Obtained PPG and/or ECG signal segments can be provided to the model(s) to update the model(s).Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: Salutron, Inc.Inventor: Lino Velo
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Patent number: 10265024Abstract: Technology is described for a wearable sensor system including an accelerometer and a PPG optical sensor having light processing elements including at least one photodetector in at least one linear configuration sharing an axis of orientation with the accelerometer. Heart rate measurements determined from reflected light detected by a photodetector of the light processing elements in a linear configuration are co-sampled with accelerometer measurements for one of its axes sharing its orientation with the linear configuration, thus providing per axis measurements which provide more precise data points for more easily compensating for motion artifacts in heart rate data. A wrist wearable biometric monitoring device is also described which embodies the wearable sensor system and performs active motion artifact compensation.Type: GrantFiled: July 26, 2014Date of Patent: April 23, 2019Assignee: Salutron, Inc.Inventors: Yong Jin Lee, Lino Velo
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Publication number: 20160022220Abstract: Technology is described for a wearable sensor system including an accelerometer and a PPG optical sensor having light processing elements including at least one photodetector in at least one linear configuration sharing an axis of orientation with the accelerometer. Heart rate measurements determined from reflected light detected by a photodetector of the light processing elements in a linear configuration are co-sampled with accelerometer measurements for one of its axes sharing its orientation with the linear configuration, thus providing per axis measurements which provide more precise data points for more easily compensating for motion artifacts in heart rate data. A wrist wearable biometric monitoring device is also described which embodies the wearable sensor system and performs active motion artifact compensation.Type: ApplicationFiled: July 26, 2014Publication date: January 28, 2016Inventors: Yong Jin Lee, Lino Velo
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Patent number: 6812126Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and time. The barrier can comprises a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: April 21, 2000Date of Patent: November 2, 2004Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Randhir S. Bubber, Lino A. Velo
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Patent number: 6645847Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: January 30, 2002Date of Patent: November 11, 2003Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
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Patent number: 6627995Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: April 1, 2002Date of Patent: September 30, 2003Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
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Patent number: 6461675Abstract: Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput.Type: GrantFiled: July 10, 1998Date of Patent: October 8, 2002Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., Zeming Liu, Guihua Shang
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Publication number: 20020137332Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: ApplicationFiled: April 1, 2002Publication date: September 26, 2002Applicant: CVC Products, Inc., a Delware corporationInventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, David M. Leet, Sanjay Gopinath
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Publication number: 20020102838Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: ApplicationFiled: January 30, 2002Publication date: August 1, 2002Applicant: CVC Products, Inc., a Delaware corporationInventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, David M. Leet, Sanjay Gopinath
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Patent number: 6365502Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: March 3, 2000Date of Patent: April 2, 2002Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
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Publication number: 20020006468Abstract: Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput.Type: ApplicationFiled: July 10, 1998Publication date: January 17, 2002Inventors: AJIT P. PARANJPE, MEHRDAD M. MOSLEHI, LINO A. VELO, THOMAS R. OMSTEAD, DAVID R. CAMPBELL, ZEMING LIU, GUIHUA SHANG
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Patent number: 6294836Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and tin. The barrier can comprise a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization in one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: December 22, 1998Date of Patent: September 25, 2001Assignee: CVC Products Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Randhir S. Bubber, Lino A. Velo
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Patent number: 6204204Abstract: A method and apparatus are disclosed for depositing a tantalum-containing diffusion barrier, such as a TaN barrier layer, by dissolving a tantalum-bearing organometallic precursor, such as PEMAT or PDEAT, in an inert, low viscosity, high molecular weight, low volatility solvent, such as octane, heptane, decane or toluene. The precursor-solvent solution is vaporized and flowed over a substrate to deposit the barrier. The precursor solution has a viscosity substantially similar to that of the solvent by maintaining the ratio of precursor to solvent at a generally low value, such as approximately 10% precursor. The boiling point of the solvent is substantially similar to the boiling point of the precursor, such as within 50% of the precursor boiling point at one atmosphere, to enhance repeatability of barrier film quality.Type: GrantFiled: April 1, 1999Date of Patent: March 20, 2001Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Randhir S. Bubber, Lino A. Velo
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Patent number: 5326170Abstract: A method for calibrating at least one temperature sensor. A wafer (30) having calibration structures of a material having a melting point in the range of 150.degree. to 1150.degree. C. is provided. The temperature sensor is operable to detect a temperature dependent characteristic of the wafer and output a signal corresponding to the temperature depending characteristic. The power input is selectively varied and the wafer temperature is ramped for a calibration run. A wafer characteristic, such as wafer reflectance, radiance, or emissivity, is monitored. A first step change in the wafer characteristic corresponding to a wafer temperature equal to the melting point of the calibration structures is detected and a set of calibration parameters for each temperature sensor being calibrated is calculated.Type: GrantFiled: September 1, 1993Date of Patent: July 5, 1994Assignee: Texas Instruments, IncorporatedInventors: Mehrdad M. Moslehi, Habib Najm, Lino A. Velo
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Patent number: 5305417Abstract: In a RTP reactor where wafer temperature is measured by a pyrometer assembly (32), a pyrometer assembly (50) is further provided to measure the temperature of the quartz window (30) that is situated between the wafer pyrometer assembly (32) and the wafer (16) that is being processed. During the calibration procedure (100, 120) where a thermocouple wafer is used, the measurements from the wafer pyrometer assembly (32) and the window pyrometer assembly (50) are calibrated, and pyrometer measurements and thermocouple measurements are collected and compiled into calibration tables. During actual RTP reactor operation, the data from the calibration tables and current wafer and window pyrometer measurements are used to compute corrected wafer temperature(s). The corrected wafer temperature(s) is/are then used to control the intensities of the heating lamps according to the wafer processing heating schedule.Type: GrantFiled: March 26, 1993Date of Patent: April 19, 1994Assignee: Texas Instruments IncorporatedInventors: Habib N. Najm, Mehrdad M. Moslehi, Somnath Banerjee, Lino A. Velo
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Patent number: 5296385Abstract: Several process flows are proposed for achieving suitable wafer backside structures for integrated RTP-based device processing. The wafer backside conditions proposed here can be adapted for integrated fabrication process flows based on multiple integrated single-wafer and rapid thermal processing (RTP) cycles. These backside conditions ensure repeatable RTP uniformity and accurate pyrometry calibrations and measurements. The use of a highly doped layer near the wafer backside ensures negligible infrared transmission and repeatable RTP-based process uniformity, both for the high-temperature and the lower temperature RTP-based processes such as low-pressure chemical-vapor deposition of silicon. Two backside layers are used (oxide and nitride) to prevent dopant outdiffusion and backside oxide growth due to thermal oxidation. Moreover, the backside silicon nitride layer preserves uniform backside emissivity throughout the entire flow.Type: GrantFiled: March 3, 1992Date of Patent: March 22, 1994Assignee: Texas Instruments IncorporatedInventors: Mehrdad M. Moslehi, John Kuehne, Lino Velo