Patents by Inventor Lior Moheban
Lior Moheban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11159148Abstract: A first-in/first-out (FIFO) buffer includes at least one latch-based FIFO storage line, an input flip-flop stage upstream of the at least one latch-based storage line, an output flip-flop stage downstream of the at least one latch-based storage line. The output flip-flop stage functions as an additional storage line. Clock-gating circuitry separate from the device clock controls timing of the at least one latch-based FIFO storage line, the input flip-flop stage, and the output flip-flop stage. The input flip-flop stage functions as a second additional storage line, or as an input sampling stage. Optional bypass circuitry between the input flip-flop stage and the output flip-flop stage passes data for a storage line directly to the output flip-flop stage, without passing through the at least one latch-based storage line, when the buffer is empty.Type: GrantFiled: January 27, 2020Date of Patent: October 26, 2021Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Lior Moheban, Alex Pinskiy, Yakov Tokar
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Patent number: 10621122Abstract: Embodiments described herein provide a dual-line FIFO structure without the use of any multiplexer. Instead, the dual-line FIFO described herein uses a selectively transparent latch and a flip-flop serially connected to the latch, such that the combination of the serially connected latch and the flip-flop can temporarily store up to two data units at two clock cycles.Type: GrantFiled: May 14, 2018Date of Patent: April 14, 2020Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Lior Moheban, Ronen Goldberg, Yakov Tokar, Gregory Kovishaner, Alex Pinskiy
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Patent number: 10581433Abstract: An integrated circuit device includes dispatcher circuitry that receives signals from a first number of sources, multiplexes the signals into a single mixed signal in a predetermined order, and transmits the mixed signal to a destination via a mixed signal interface having an arbitrary length and operating at an interface clock frequency equal to a product of a device clock frequency and the first number. A second number of samplers is disposed in series along the mixed signal interface, outputting a sampled mixed signal synchronized to the interface clock. A chain of tracking elements in series, corresponding in number to the second number, outputs a tracking indication separate from the sampled mixed signal. Capture circuitry demultiplexes the sampled mixed signal into a plurality of demultiplexed signals, according to a starting point based on the tracking indication, onto a plurality of signal buses corresponding in number to the first number.Type: GrantFiled: September 10, 2019Date of Patent: March 3, 2020Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Lior Moheban, Jacob Jul Schroder, Yuval Peled
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Patent number: 9459651Abstract: A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one.Type: GrantFiled: November 4, 2011Date of Patent: October 4, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Lior Moheban, Avi Elazary, Amir Nave, Noam Sivan
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Patent number: 9038006Abstract: A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.Type: GrantFiled: April 30, 2013Date of Patent: May 19, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Lior Moheban, Asher Berkovitz, Guy Shmueli
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Publication number: 20140325461Abstract: A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.Type: ApplicationFiled: April 30, 2013Publication date: October 30, 2014Inventors: LIOR MOHEBAN, ASHER BERKOVITZ, GUY SHMUELI
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Publication number: 20140247080Abstract: A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one.Type: ApplicationFiled: November 4, 2011Publication date: September 4, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Lior Moheban, Avi Elazary, Amir Nave, Noam Sivan
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Patent number: 8302065Abstract: A device that includes a core and a wrapper. The wrapper includes at least one shared wrapper cell that is shared by a group of core pins that belong to a single clock domain. A method for designing a wrapper. The method includes receiving design information representative of a design of a core, locating a group of mutually independent core pins that belong to a single clock domain; and designing a shared wrapped cell that is shared by the group of core pins.Type: GrantFiled: March 13, 2006Date of Patent: October 30, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Oshri Shomrony, Aner Kantor, Lior Moheban, Ytzhak Rosenthal
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Patent number: 8286040Abstract: A device having testing capabilities, the device includes: a tested circuit that includes multiple scan chains; a compactor adapted to compress scan chain test responses; a mask unit, connected between the multiple scan chains and the compactor, wherein the mask unit is adapted to mask scan chain test responses outputted by the multiple scan chains during a masking period; and an mask prevention unit, adapted to prevent masking of scan chain test responses during a mask prevention period that at least partially overlaps a mask unit configuration period.Type: GrantFiled: February 9, 2007Date of Patent: October 9, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Gal Malach, Nir Blinky, Lior Moheban
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Publication number: 20100090706Abstract: A device having testing capabilities, the device includes: a tested circuit that includes multiple scan chains; a compactor adapted to compress scan chain test responses; a mask unit, connected between the multiple scan chains and the compactor, wherein the mask unit is adapted to mask scan chain test responses outputted by the multiple scan chains during a masking period; and an mask prevention unit, adapted to prevent masking of scan chain test responses during a mask prevention period that at least partially overlaps a mask unit configuration period.Type: ApplicationFiled: February 9, 2007Publication date: April 15, 2010Applicant: FREESCALE SEMICONDUCTOR ,INC.Inventors: Gal Malach, Nir Blinky, Lior Moheban
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Publication number: 20090206866Abstract: A device that includes a core and a wrapper. The wrapper includes at least one shared wrapper cell that is shared by a group of core pins that belong to a single clock domain. A method for designing a wrapper. The method includes receiving design information representative of a design of a core, locating a group of mutually independent core pins that belong to a single clock domain; and designing a shared wrapped cell that is shared by the group of core pins.Type: ApplicationFiled: March 12, 2006Publication date: August 20, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Oshri Shomrony, Aner Kantor, Lior Moheban, Ytzhak Rosenthal