Patents by Inventor Lipen YUAN

Lipen YUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210217744
    Abstract: A semiconductor device includes a first transistor having a first fin, wherein a base of the first fin is surrounded by a first dielectric material, the first fin having a first fin height measured from the top surface of the first dielectric material to a top surface of the first fin; and a second transistor having a second fin, wherein a base of the second fin is surrounded by a second dielectric material, the second fin having a second fin height measured from a top surface of the second dielectric material to a top surface of the second fin, wherein the first fin height is different from the second fin height.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 15, 2021
    Inventors: Wei-Cheng LIN, Hui-Ting YANG, Jiann-Tyng TZENG, Lipen YUAN, Wei-An LAI
  • Publication number: 20210110094
    Abstract: A method of manufacturing a semiconductor device that includes identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities; relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights. The method also includes replacing cells in the first row which have the H1 height with corresponding substitute cells, each substitute cell being correspondingly taller relative to the second direction and correspondingly narrower relative to the first direction, the replacing thereby increasing a density of the second row at least without substantially increasing a density of the first row.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Wei-Cheng LIN, Hui-Ting YANG, Jiann-Tyng TZENG, Lipen YUAN, Wei-An LAI
  • Patent number: 10964684
    Abstract: A method of modifying an integrated circuit includes operations related to identifying at least two fin-containing functional areas of the integrated circuit, generating a performance curve for each fin-containing functional area of the integrated circuit for each fin height of a series of fin heights, and determining whether an inflection point exists for each performance curve. The method further includes operations related to selecting a value of a performance characteristic for each of the fin-containing functional areas, the selected value having a corresponding fin height in each of the fin-containing functional areas, modifying each fin-containing functional area to have the fin height corresponding to the selected value of the performance characteristic; and combining the modified fin-containing functional areas to form a modified integrated circuit.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Cheng Lin, Hui-Ting Yang, Jiann-Tyng Tzeng, Lipen Yuan, Wei-An Lai
  • Patent number: 10923426
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Publication number: 20210005633
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Publication number: 20210005634
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Publication number: 20200411503
    Abstract: An integrated circuit includes a first region. The integrated circuit further includes a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first region or the second region, wherein the power structure includes a second conductive structure overlapping a boundary between the first region and the second region, the first conductive structure and the second conductive structure are aligned in a second direction different than the first direction, and the first conductive structure and the second conductive structure are separated from each other in the first direction.
    Type: Application
    Filed: September 16, 2020
    Publication date: December 31, 2020
    Inventors: Fong-Yuan CHANG, Jyun-Hao CHANG, Sheng-Hsiung CHEN, Po-Hsiang HUANG, Lipen YUAN
  • Patent number: 10878158
    Abstract: A method of generating a layout diagram includes: identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities; relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights; for a first one of the cells having H1 height (a first H1 cell) in a first location in the first row, substituting a multi-row-height cell for the first H1 cell, the multi-row-height cell being narrower than the first H1 cell relative to the first direction; and placing a first part of the multi-row-height cell into a portion of the first location resulting in the first and second rows having more similar cell densities.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Hui-Ting Yang, Jiann-Tyng Tzeng, Lipen Yuan, Wei-An Lai
  • Patent number: 10797041
    Abstract: An integrated circuit includes a first region and a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a first via coupled to the first conductive structure. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first or second region. The power structure includes a second conductive structure extending in the first direction and overlapping a boundary between the first region and the second region. The first conductive structure and the second conductive structure are aligned in a second direction. The first conductive structure and the second conductive structure are separated from each other in the first direction by a distance greater than a minimum spacing requirement of the first conductive structure and the second conductive structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Lipen Yuan
  • Patent number: 10797078
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Publication number: 20200243446
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions within a substrate. A gate structure is over the substrate between the first and second source/drain regions. A middle-end-of-the-line (MEOL) structure is over the second source/drain region. The MEOL structure has a bottommost surface that continuously extends in a first direction from directly contacting a top of the second source/drain region to laterally past an outer edge of the second source/drain region. A conductive structure is on the MEOL structure. A second gate structure is separated from the gate structure by the second source/drain region. The conductive structure continuously extends in a second direction over the MEOL structure and past opposing sides of the second gate structure. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the MEOL structure along through the conductive structure.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Patent number: 10672708
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Publication number: 20200105660
    Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.
    Type: Application
    Filed: August 28, 2019
    Publication date: April 2, 2020
    Inventors: Kam-Tou SIO, Cheng-Chi CHUANG, Chih-Ming LAI, Jiann-Tyng TZENG, Wei-Cheng LIN, Lipen YUAN
  • Publication number: 20200058681
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Publication number: 20200019667
    Abstract: A method of generating a layout diagram includes: identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities; relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights; for a first one of the cells having H1 height (a first H1 cell) in a first location in the first row, substituting a multi-row-height cell for the first H1 cell, the multi-row-height cell being narrower than the first H1 cell relative to the first direction; and placing a first part of the multi-row-height cell into a portion of the first location resulting in the first and second rows having more similar cell densities.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 16, 2020
    Inventors: Wei-Cheng LIN, Hui-Ting YANG, Jiann-Tyng TZENG, Lipen YUAN, Wei-An LAI
  • Publication number: 20200006318
    Abstract: A method of modifying an integrated circuit includes operations related to identifying at least two fin-containing functional areas of the integrated circuit, generating a performance curve for each fin-containing functional area of the integrated circuit for each fin height of a series of fin heights, and determining whether an inflection point exists for each performance curve. The method further includes operations related to selecting a value of a performance characteristic for each of the fin-containing functional areas, the selected value having a corresponding fin height in each of the fin-containing functional areas, modifying each fin-containing functional area to have the fin height corresponding to the selected value of the performance characteristic; and combining the modified fin-containing functional areas to form a modified integrated circuit.
    Type: Application
    Filed: May 7, 2019
    Publication date: January 2, 2020
    Inventors: Wei-Cheng LIN, Hui-Tang YANG, Jiann-Tyng TZENG, Lipen YUAN, Wei-An LAI
  • Patent number: 10262981
    Abstract: A method of forming an integrated circuit is disclosed. The method includes generating, by a processor, a layout design of the integrated circuit, outputting the integrated circuit based on the layout design, and removing a portion of a conductive structure of the integrated circuit to form a first conductive structure and a second conductive structure. Generating the layout design includes generating a standard cell layout having a set of conductive feature layout patterns, placing a power layout pattern with the standard cell layout according to at least one design criterion, and extending at least one conductive feature layout pattern of the set of conductive feature layout patterns in at least one direction to a boundary of the power layout pattern. The power layout pattern includes a cut feature layout pattern. The cut feature layout pattern identifies a location of the removed portion of the conductive structure of the integrated circuit.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: April 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Lipen Yuan
  • Publication number: 20190096872
    Abstract: An integrated circuit includes a first region and a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a first via coupled to the first conductive structure. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first or second region. The power structure includes a second conductive structure extending in the first direction and overlapping a boundary between the first region and the second region. The first conductive structure and the second conductive structure are aligned in a second direction. The first conductive structure and the second conductive structure are separated from each other in the first direction by a distance greater than a minimum spacing requirement of the first conductive structure and the second conductive structure.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventors: Fong-Yuan CHANG, Jyun-Hao CHANG, Sheng-Hsiung CHEN, Po-Hsiang HUANG, Lipen YUAN
  • Publication number: 20180350743
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 6, 2018
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Patent number: 9964977
    Abstract: A device is disclosed that includes a delay circuit, a detection circuit, and a bias circuit. The delay circuit is configured to generate an oscillating signal in response to a reference signal, a first bias voltage, and a second bias voltage. The detection circuit is configured to compare the oscillating signal with the reference signal, to generate a detect signal. The bias circuit is configured to adjust the first bias voltage and the second bias voltage according to the detect signal and a reference voltage.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 8, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chung Tseng, Lipen Yuan, Jhih-Jie Shao, Chien-Jung Li