Abstract: A pressure indicating device for detecting and isolating leakage of toxic and/or pyrophoric gasses from within various packages is disclosed. The device can affix to a user port of a cylinder package. The device has a flexible disc-like structure which is fine tuned to outwardly flex in response to a build-up of pressure of the gas exerted against the disc-like structure. The flexed disc contacts a movable pin and pushes the push outwards from within the device. The outward movement of the pin pierces a paper seal extending over the device, thereby indicating a leak from within the valving of the package. The device withstands the pressure exerted against it, thereby also isolating the leak of the pressurized gas.

Abstract: A pressure indicating device for detecting and isolating leakage of toxic and/or pyrophoric gasses from within various packages is disclosed. The device can affix to a user port of a cylinder package. The device has a flexible disc-like structure which is fine tuned to outwardly flex in response to a build-up of pressure of the gas exerted against the disc-like structure. The flexed disc contacts a movable pin and pushes the push outwards from within the device. The outward movement of the pin pierces a paper seal extending over the device, thereby indicating a leak from within the valving of the package. The device withstands the pressure exerted against it, thereby also isolating the leak of the pressurized gas.

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Abstract: A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield.

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Abstract: A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield.

Abstract: Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C4 solder bump openings therethrough with the shape of C4 solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C4 solder bump openings to form through holes in the conductive metal layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. As an option, form a barrier layer over the plating sites next.

Abstract: Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C4 solder bump openings therethrough with the shape of C4 solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C4 solder bump openings to form through holes in the conductive metal layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. As an option, form a barrier layer over the plating sites next.

Abstract: A method of improving the uniformity of etching of a film on an article, the method including the steps of immersing the article containing the film into a tank of etchant, rotating the article while in the etchant for a desired amount of time so as to cause improved uniformity of etching of the film compared to etching without rotating the article, and removing the article from the tank of etchant. In a preferred embodiment of the invention, the article is a semiconductor wafer.

Abstract: An aqueous electrochemical etchant for etching metals in the presence of one or more metals not to be etched, the etchant including glycerol in the concentration range of 1.30 to 1.70 M, a sulfate compound having a sulfate ion concentration in the range of 0 to 0.5 M, and a phosphate compound having a phosphate ion concentration in the range of 0.1 to 0.5 M.

Abstract: An apparatus for and method of minimizing the thermo-mechanical fatigue of flip-chip packages. The interposer of the present invention, preferably comprising an organic polymer such as polyimide, contains apertures having conductive plugs inserted therein for joining a chip to a substrate in an electronic module utilizing flip-chip packaging. The interposer is selected to provide optimum spacing between the chip and substrate having a coefficient of thermal expansion adapted to the thermal cycling temperature extremes of the module components. The interposer may comprise an inner core with two adhesive outer layers which may comprise different materials to promote adhesion at their respective interfaces within a module. Conductive plugs are disposed within the apertures of the interposer comprising of a first and second solder or comprising a conductive plug having top and bottom surfaces coated with a conductive adhesive.

Abstract: A process and etchant solution for chemical wet etching of thin film metals in the presence of a protected metal. The etching solution has a pH range of about 2.7 to 4.0. The etching solution may include hydrogen peroxide, potassium sulfate, and potassium EDTA, and it reduces or eliminates the incidence of etch-resistant metal without damaging the protected metal.

Abstract: A process and etchant solution for chemical wet etching of thin film metals in the presence of a protected metal. The etching solution has a pH range of about 2.7 to 4.0. The etching solution may include hydrogen peroxide, potassium sulfate, and potassium EDTA, and it reduces or eliminates the incidence of etch-resistant metal without damaging the protected metal.

Abstract: A process and assembly for stabilizing organic additives in an electrolytic solution while electroplating copper. The process includes forming a protective film on a first surface of an anode and minimizing contact between the electrolytic solution and a second surface of the anode which is further from the cathode than the first surface. An anode housing is used to minimize contact between the electrolytic solution and the second surface of the anode. The housing includes two side walls and a bottom wall, each having a groove, and a sealing back plate. The anode is fitted in the grooves such that the first surface of the anode is in contact with the electrolytic solution and the second surface of the anode abuts against the sealing back plate. The anode housing may be used in an electroplating system including the anode housing, a plating tank containing the electrolytic solution, a cathode immersed in the electrolytic solution, and an anode, which preferably is in the shape of a slab.

Abstract: A process and assembly for stabilizing organic additives in an electrolytic solution while electroplating copper. The process includes forming a protective film on a first surface of an anode and minimizing contact between the electrolytic solution and a second surface of the anode which is further from the cathode than the first surface. An anode housing is used to minimize contact between the electrolytic solution and the second surface of the anode. The housing includes two side walls and a bottom wall, each having a groove, and a sealing back plate. The anode is fitted in the grooves such that the first surface of the anode is in contact with the electrolytic solution and the second surface of the anode abuts against the sealing back plate. The anode housing may be used in an electroplating system including the anode housing, a plating tank containing the electrolytic solution, a cathode immersed in the electrolytic solution, and an anode, which preferably is in the shape of a slab.

Abstract: A process for wet chemically stripping dry, thick film photoresists in semiconductor applications. This process includes contacting the silicon wafer with a stripping solution and agitating the solution. The process may be performed in a strip tank having a chemical stripping solution, and nitrogen or other inert gases may be provided through a pressurized tube to cause bubbling in the solution and to strip the wafer.