Patents by Inventor Lizabeth Keser
Lizabeth Keser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955395Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.Type: GrantFiled: June 30, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
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Publication number: 20230317620Abstract: Various embodiments disclosed relate to a semiconductor assembly having a ceramic or glass interposer for connecting dies within a semiconductor package. The present disclosure includes a ceramic or glass interposer having a carrier layer of substantially glass or ceramic material and a connecting layer having at least one dielectric layer and electrical routing therein.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Carlton Hanna, Georg Seidemann, Eduardo De Mesa, Abdallah Bacha, Lizabeth Keser
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Publication number: 20230317618Abstract: An electronic device comprises a substrate including an organic material; a glass bridge die included in the substrate, the glass bridge die including electrically conductive interconnect; and a first integrated circuit (IC) die and at least a second IC die arranged on a surface of the substrate and including bonding pads connected to the interconnect of the glass bridge die.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Carlton Hanna, Georg Seidemann, Eduardo De Mesa, Abdallah Bacha, Lizabeth Keser
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Publication number: 20230317582Abstract: An electronic device comprises a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material; a stiffening layer including one of a ceramic or glass, the stiffening layer including a first surface contacting a first surface of the first RDL and including a through layer via (TLV); and multiple integrated circuit (ICs) arranged on a second surface of the first RDL and including bonding pads, wherein the conductive traces of the first RDL provide electrical continuity between at least one bonding pad of the ICs and at least one TLV of the stiffening layer.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Carlton Hanna, Georg Seidemann, Eduardo De Mesa, Abdallah Bacha, Lizabeth Keser
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Publication number: 20230317551Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Vishnu Prasad, Abdallah Bacha, Mohan Prashanth Javare Gowda, Lizabeth Keser, Thomas Wagner, Bernd Waidhas, Sonja Koller, Eduardo De Mesa, Jan Proschwitz
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Publication number: 20230317681Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Sonja Koller, Vishnu Prasad, Bernd Waidhas, Eduardo De Mesa, Lizabeth Keser, Thomas Wagner, Mohan Prashanth Javare Gowda, Abdallah Bacha, Jan Proschwitz
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Publication number: 20230317705Abstract: An electronic system has a printed circuit board and a substrate. The substrate has two sides, a top and bottom. At least one memory unit is connected to the bottom side of the substrate and at least one processor is connected to the top side of the substrate. The memory is connected to the processor with interconnects that pass through the substrate.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Carlton Hanna, Bernd Waidhas, Georg Seidemann, Stephan Stoeckl, Pouya Talebbeydokhti, Stefan Reif, Eduardo De Mesa, Abdallah Bacha, Mohan Prashanth Javare Gowda, Lizabeth Keser
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Publication number: 20230282615Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.Type: ApplicationFiled: March 3, 2022Publication date: September 7, 2023Applicant: Intel CorporationInventors: Thomas Wagner, Abdallah Bacha, Vishnu Prasad, Mohan Prashanth Javare Gowda, Bernd Waidhas, Sonja Koller, Eduardo De Mesa, Jan Proschwitz, Lizabeth Keser
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Publication number: 20230090265Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.Type: ApplicationFiled: November 21, 2022Publication date: March 23, 2023Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
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Patent number: 11581287Abstract: Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.Type: GrantFiled: June 29, 2018Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Robert Sankman, Sanka Ganesan, Bernd Waidhas, Thomas Wagner, Lizabeth Keser
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Publication number: 20220415815Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Bernd Waidhas, Carlton Hanna, Stephen Morein, Lizabeth Keser, Georg Seidemann
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Publication number: 20220415806Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Bernd Waidhas, Carlton Hanna, Stephen Morein, Lizabeth Keser, Georg Seidemann
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Publication number: 20220415814Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component embedded in an insulating material on the surface of the package substrate and including a TSV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the insulating material including a second conductive pathway electrically coupled to the TSV; and a second microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TSV, the second microelectronic component, and the first microelectronic component.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventors: Bernd Waidhas, Carlton Hanna, Stephen Morein, Lizabeth Keser, Georg Seidemann
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Publication number: 20220415805Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a second microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a redistribution layer on the insulating material including a second conductive pathway electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and a wire bond electrically coupling the first and the second conductive pathways.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Bernd Waidhas, Carlton Hanna, Stephen Morein, Lizabeth Keser, Georg Seidemann
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Patent number: 11508637Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.Type: GrantFiled: April 22, 2020Date of Patent: November 22, 2022Assignee: Intel CorporationInventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
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Publication number: 20220336306Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Lizabeth KESER, Bernd WAIDHAS, Thomas ORT, Thomas WAGNER
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Patent number: 11404339Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.Type: GrantFiled: June 5, 2020Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
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Publication number: 20220051990Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.Type: ApplicationFiled: November 1, 2021Publication date: February 17, 2022Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
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Patent number: 11211337Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.Type: GrantFiled: December 4, 2019Date of Patent: December 28, 2021Assignee: Intel CorporationInventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
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Publication number: 20200303274Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.Type: ApplicationFiled: June 5, 2020Publication date: September 24, 2020Inventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner