Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

Abstract: Provided is a fabricating method of a semiconductor device, including the following. Fin structures are formed on a substrate, and the adjacent fin structures have an opening therebetween. A conductive material layer is formed to cover the fin structures and fill the opening. The conductive material layer and the fin structures are patterned to form a mesh structure. The mesh structure includes first strips extending in a first direction and second strips extending in a second direction. The first strips and the second strips intersect each other, and the mesh structure has holes. The first strips are located on the substrate at positions corresponding to the fin structures. The second strips are located on the substrate, and the conductive material layer in the second strips spans the fin structures. The hole is formed in the opening and surrounded by the first strips and the second strips.

Abstract: Provided is a fabricating method of a semiconductor device, including the following. Fin structures are formed on a substrate, and the adjacent fin structures have an opening therebetween. A conductive material layer is formed to cover the fin structures and fill the opening. The conductive material layer and the fin structures are patterned to form a mesh structure. The mesh structure includes first strips extending in a first direction and second strips extending in a second direction. The first strips and the second strips intersect each other, and the mesh structure has holes. The first strips are located on the substrate at positions corresponding to the fin structures. The second strips are located on the substrate, and the conductive material layer in the second strips spans the fin structures. The hole is formed in the opening and surrounded by the first strips and the second strips.

Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.

Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.

Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.

Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.

Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N?1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W?1 contact openings to create extended contact openings extending to W?1 conductive layers; 2n?1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N?1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W?1 contact openings to create extended contact openings extending to W?1 conductive layers; 2n?1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

Abstract: A semiconductor memory device includes a substrate and a plurality of rows of memory cells. The substrate comprises a plurality of isolation structures and a plurality of active regions. Each of the active regions is spaced apart from another active region by one of the isolation structures. In a cross-section of the substrate between two rows of memory cells in a direction parallel to the two rows of memory cells, a maximum height of each isolation structure with respect to a bottom of the substrate is lower than or equal to minimum heights of active regions adjacent thereto.

Abstract: An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

Abstract: An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

Abstract: A semiconductor memory device includes a substrate and a plurality of rows of memory cells. The substrate comprises a plurality of isolation structures and a plurality of active regions. Each of the active regions is spaced apart from another active region by one of the isolation structures. In a cross-section of the substrate between two rows of memory cells in a direction parallel to the two rows of memory cells, a maximum height of each isolation structure with respect to a bottom of the substrate is lower than or equal to minimum heights of active regions adjacent thereto.