Abstract: A digital delay circuit that can be readily implemented in an integrated circuit is disclosed. The circuit includes a reference clock and two or more arrays of controlled delay elements. The reference clock is passed through one array of delay elements and the thus-delayed clock is compared to an undelayed clock in a phase detector or comparator the output of which is a control voltage. The latter is applied to the control inputs of each of the delay elements. The controlled delay elements may be in the form of buffers in which the delay is varible and controlled by the level of the control input.