Patents by Inventor Louis HUTIN
Louis HUTIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200185497Abstract: A process for fabricating an electronic component with multiple quantum dots is provided, including providing a stack including a substrate, a nanostructure made of semiconductor material superposed over the substrate and including first and second quantum dots and a link linking the quantum dots, first and second control gate stacks arranged on the quantum dots, the gate stacks separated by a gap, the quantum dots and the link having a same thickness; partially thinning the link while using the gate stacks as masks to obtain the link, a thickness of which is less than that of the quantum dots; and conformally forming a dielectric layer on either side of the gate stacks so as to fill the gap above the partially thinned link. An electronic component with multiple quantum dots is also provided.Type: ApplicationFiled: November 29, 2019Publication date: June 11, 2020Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Nicolas POSSEME, Louis HUTIN, Cyrille LE ROYER, Fabrice NEMOUCHI
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Patent number: 10679139Abstract: Quantum device comprising: a quantum component forming a qubit, formed in an active layer of a substrate and comprising: a confinement region; charge carrier reservoirs; a first front gate covering the confinement region; first lateral spacers arranged around the first gate and covering access regions; an FET transistor formed in the active layer, comprising channel, source and drain regions formed in the active layer, a second front gate covering the channel region, and second lateral spacers arranged around the second front gate and covering source and drain extension regions; and wherein a width of the first lateral spacers is greater than that of the second lateral spacers.Type: GrantFiled: February 25, 2019Date of Patent: June 9, 2020Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Louis Hutin, Xavier Jehl, Maud Vinet
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Patent number: 10607993Abstract: A quantum device with spin qubits, comprising: a first semiconducting layer comprising a first matrix of data qubits and measurement qubits connected to each other through tunnel barriers; means of addressing qubits configured for controlling conduction of each tunnel barrier by the field effect and comprising: first and second conducting portions arranged in first and second superposed metallisation levels respectively; first and second conducting vias each comprising a first end connected to one of the first and second conducting portions respectively, and a second end located facing one of the tunnel barriers; a first dielectric layer interposed between the tunnel barriers and the second ends of the first and second conducting vias.Type: GrantFiled: May 1, 2018Date of Patent: March 31, 2020Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Louis Hutin, Silvano De Franceschi, Tristan Meunier, Maud Vinet
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Publication number: 20190371926Abstract: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.Type: ApplicationFiled: May 16, 2019Publication date: December 5, 2019Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Louis HUTIN, Sylvain BARRAUD, Benoit BERTRAND, Maud VINET
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Publication number: 20190371908Abstract: A method of fabricating an electronic component with multiple quantum islands is provided, including supplying a substrate on which rests a nanowire made of semiconductor material not intentionally doped, the nanowire having at least two main control gates resting thereon so as to form respective qubits in the nanowire under the two main control gates, the two main control gates being separated by a groove, top and lateral faces of the two main control gates and a bottom of the groove being covered by a dielectric layer; depositing a conductive material in the groove and on the top of the two main control gates; and planarizing down to the dielectric layer on the top of the two main control gates, so as to obtain an element made of conductive material self-aligned between the main control gates.Type: ApplicationFiled: May 16, 2019Publication date: December 5, 2019Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Louis HUTIN, Sylvain BARRAUD, Benoit BERTRAND, Maud VINET
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Publication number: 20190266509Abstract: Quantum device comprising: a quantum component forming a qubit, formed in an active layer of a substrate and comprising: a confinement region; charge carrier reservoirs; a first front gate covering the confinement region; first lateral spacers arranged around the first gate and covering access regions; an FET transistor formed in the active layer, comprising channel, source and drain regions formed in the active layer, a second front gate covering the channel region, and second lateral spacers arranged around the second front gate and covering source and drain extension regions; and wherein a width of the first lateral spacers is greater than that of the second lateral spacers.Type: ApplicationFiled: February 25, 2019Publication date: August 29, 2019Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Louis HUTIN, Xavier Jehl, Maud Vinet
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Publication number: 20190123183Abstract: A quantum device with spin qubits, comprising: a semiconductor portion arranged on a buried dielectric layer of a semiconductor-on-insulator substrate also including a semiconductor support layer, wherein first distinct parts each form a confinement region of one of the qubits and are spaced apart from one another by a second part forming a coupling region between the confinement regions of the qubits; front gates each at least partially covering one of the first parts of the semiconductor portion; and wherein the support layer comprises a doped region a part of which is arranged in line with the second part of the semiconductor portion and is self-aligned with respect to the front gates, and forms a back gate controlling the coupling between the confinement regions of the qubits.Type: ApplicationFiled: October 15, 2018Publication date: April 25, 2019Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Louis HUTIN, Xavier JEHL, Maud VINET
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Publication number: 20180331108Abstract: A quantum device with spin qubits, comprising: a first semiconducting layer comprising a first matrix of data qubits and measurement qubits connected to each other through tunnel barriers; means of addressing qubits configured for controlling conduction of each tunnel barrier by the field effect and comprising: first and second conducting portions arranged in first and second superposed metallisation levels respectively; first and second conducting vias each comprising a first end connected to one of the first and second conducting portions respectively, and a second end located facing one of the tunnel barriers; a first dielectric layer interposed between the tunnel barriers and the second ends of the first and second conducting vias.Type: ApplicationFiled: May 1, 2018Publication date: November 15, 2018Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Louis Hutin, Silvano De Franceschi, Tristan Meunier, Maud Vinet
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Patent number: 9911827Abstract: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.Type: GrantFiled: December 8, 2016Date of Patent: March 6, 2018Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, ST Microelectronics SA, ST Microelectronics (Crolles 2) SASInventors: Louis Hutin, Julien Borrel, Yves Morand, Fabrice Nemouchi
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Patent number: 9911841Abstract: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.Type: GrantFiled: March 10, 2016Date of Patent: March 6, 2018Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Sylvain Barraud, Ivan Duchemin, Louis Hutin, Yann-Michel Niquet, Maud Vinet
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Patent number: 9911820Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk?tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.Type: GrantFiled: March 21, 2017Date of Patent: March 6, 2018Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Cyrille Le Royer, Frederic Boeuf, Laurent Grenouillet, Louis Hutin, Yves Morand
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Patent number: 9831319Abstract: A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.Type: GrantFiled: March 2, 2016Date of Patent: November 28, 2017Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Julien Borrel, Louis Hutin, Yves Morand, Fabrice Nemouchi, Heimanu Niebojewski
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Publication number: 20170271470Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk?tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.Type: ApplicationFiled: March 21, 2017Publication date: September 21, 2017Applicants: Commissariat a I'energie atomique et aux energies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Cyrille LE ROYER, Frederic Boeuf, Laurent Grenouillet, Louis Hutin, Yves Morand
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Publication number: 20170162672Abstract: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.Type: ApplicationFiled: December 8, 2016Publication date: June 8, 2017Applicants: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Louis HUTIN, Julien BORREL, Yves MORAND, Fabrice NEMOUCHI
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Patent number: 9536951Abstract: FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate.Type: GrantFiled: September 9, 2015Date of Patent: January 3, 2017Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Sylvain Maitrejean, Emmanuel Augendre, Louis Hutin, Yves Morand
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Publication number: 20160268406Abstract: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.Type: ApplicationFiled: March 10, 2016Publication date: September 15, 2016Applicant: Commissariat a L'Energie Atomique et aux Energies AlternativesInventors: Sylvain BARRAUD, Ivan DUCHEMIN, Louis HUTIN, Yann-Michel NIQUET, Maud VINET
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Publication number: 20160260819Abstract: A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.Type: ApplicationFiled: March 2, 2016Publication date: September 8, 2016Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Julien BORREL, Louis Hutin, Yves Morand, Fabrice Nemouchi, Heimanu Niebojewski
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Publication number: 20160071933Abstract: FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate.Type: ApplicationFiled: September 9, 2015Publication date: March 10, 2016Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Sylvain MAITREJEAN, Emmanuel AUGENDRE, Louis HUTIN, Yves MORAND