Patents by Inventor Luciano Gandolfi

Luciano Gandolfi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5038198
    Abstract: A modular semiconductor power device has a conductive member consisting of an alumina plate to which copper layers are soldered on opposite sides. A chip is soldered to one of these layers and the other of these layers is soldered in turn to a metal heat sink. The chip is connected to respective copper strips which, in turn, are soldered to thermal strips originally forming part of a frame so that, after the device is encapsulated in a synthetic resin, the connecting members of the frame can be cut away to leave free ends of the latter strips exposed.
    Type: Grant
    Filed: January 9, 1990
    Date of Patent: August 6, 1991
    Assignee: SGS-Thomson Microelectronics S.p.A.
    Inventors: Antonio Perniciaro Spatrisano, Luciano Gandolfi, Carlo Minotti, Natale Di Cristina
  • Patent number: 4926547
    Abstract: The components used in the method comprise a heat-dissipating base plate, one or more three-layer plates (the top layer consisting of copper plates and strips) and a one-piece frame designed to constitute the terminals. After the chips have been soldered onto the upper plates and connected to the strips, the inner ends of the frame are soldered to points of connection with the chips. This is followed by the encapsulation in resin and the shearing of the outer portions of the frame, which, during the process, serve to temporarily connect the terminals.
    Type: Grant
    Filed: June 27, 1989
    Date of Patent: May 22, 1990
    Assignee: SGS-Thomson Microelectronics S.p.A.
    Inventors: Antonio P. Spatrisano, Luciano Gandolfi, Carlo Minotti, Natale Di Cristina
  • Patent number: 4881117
    Abstract: A multiplicity of semiconductor chips constituting the active elements of a semiconductor power device are attached, in a predetermined configuration, to a metal plate which acts as both a support and a first electrical terminal. Two other electrical terminals are formed by two metal electrodes having an interdigitated structure with the fingers of one electrode being inserted between those of the other electrode and which are positioned above the semiconductor chips and have tabs for establishing a connection between the electrodes and the two contact areas of each chip.
    Type: Grant
    Filed: February 23, 1984
    Date of Patent: November 14, 1989
    Assignee: SGS-ATES Componenti Elettronici S.p.A.
    Inventors: Luciano Gandolfi, Giuseppe Ferla
  • Patent number: 4805004
    Abstract: A semiconductor device with a planar junction and self-passivating termination includes: a silicon substrate of one type of conductivity; an epitaxial layer of a second type of conductivity which is opposite to the first type of conductivity, lying on the substrate, so as to form with it a planar PN junction; a first region, of the first type of conductivity, that delimits, in its interior, an active portion of the device and extends transversely, from the surface of the epitaxial layer to the substrate with a portion having a high concentration of impurities and, on the surface, in the epitaxial layer, with a portion having a low concentration of impurities; and another region immersed in the epitaxial layer and of the same type of conductivity, but with a higher concentration of impurities. The latter region and the top portion of the first region extend toward each other with progressively decreasing concentrations of impurities.
    Type: Grant
    Filed: December 11, 1986
    Date of Patent: February 14, 1989
    Assignee: SGS Microelettronica SpA
    Inventors: Luciano Gandolfi, Salvatore Musumeci
  • Patent number: 4615478
    Abstract: After the support of not-noble metal has suitably been heated and before and during the application of a tablet of soldering material destined to receive the semiconductor chip, the soldering area is engaged by a reducing gas flame (for example, 20% hydrogen and 80% nitrogen at a temperature lower than 570.degree. C.), which eliminates any oxidation products. The soldering is thus of very good quality without using the normal plating of noble metal.
    Type: Grant
    Filed: June 10, 1983
    Date of Patent: October 7, 1986
    Assignee: SGS-ATES Componenti Elettronici S.p.A.
    Inventors: Luciano Gandolfi, Antonio Grasso, Antonio Perniciaro
  • Patent number: 4176443
    Abstract: A silicon wafer, having a front surface with disjointed contact areas and a uniform rear surface, is provided at the contact areas of its front surface with respective pads each comprising a base layer of aluminum, a first intermediate layer of chromium or titanium, a second intermediate layer of nickel and an outer layer of gold or palladium. The rear surface is covered with a base layer of gold (or of a gold/arsenic alloy in the case of N-type silicon), a first intermediate layer of chromium, a second intermediate layer of nickel and an outer layer of gold or palladium to which a film of low-melting bonding agent (lead/tin solder) is applied. After testing and elimination of unsatisfactory wafer sections, the remaining sections are separated into dies placed on a conductive substrate; an extremity of a respective terminal lead, encased in a similar bonding agent, is then placed on the outer layer of each contact pad. All soldering operations are simultaneously performed in a furnace.
    Type: Grant
    Filed: November 3, 1978
    Date of Patent: December 4, 1979
    Assignee: SGS-ATES Componenti Elettronici S.p.A.
    Inventors: Giulio Iannuzzi, Carlo C. deMartiis, Vittorio Del Bo, Luciano Gandolfi
  • Patent number: 4126931
    Abstract: Several junction-type semiconductor chips, specifically NPN transistors, are simultaneously produced by mesa technique from a semiconductor wafer by adhering to one major surface thereo a supporting structure including a bonding layer of wax, similarly adhering a protective layer of a relatively soft material -- likewise a wax -- to the opposite major wafer surface, and dividing the wafer into chips temporarily held together by the supporting structure. The last-mentioned step involves a splitting of the protective layer into isolated sections by making incisions in that layer cutting into the underlying wafer body, followed by an erosion of the semiconductor material of that body by an etching solution to form channels which extend completely across the wafer and terminate at the supporting structure, these channels being widened in the immediate vicinity of the protective layer to form undercuts. A continuous passivating film is applied, e.g.
    Type: Grant
    Filed: April 11, 1977
    Date of Patent: November 28, 1978
    Assignee: SGS-ATES Componenti Elettronici S.p.A.
    Inventors: Luciano Gandolfi, Rudolf Rocak
  • Patent number: RE37416
    Abstract: The components used in the method comprise a heat-dissipating base plate, one or more three-layer plates (the top layer consisting of copper plates and strips) and a one-piece frame designed to constitute the terminals. After the chips have been soldered onto the upper plates and connected to the strips, the inner ends of the frame are soldered to points of connection with the chips. This is followed by the encapsulation in resin and the shearing of the outer portions of the frame, which, during the process, serve to temporarily connect the terminals.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: October 23, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonio P. Spatrisano, Luciano Gandolfi, Carlo Minotti, Natale Di Cristina
  • Patent number: RE38037
    Abstract: A modular semiconductor power device has a conductive member consisting of an alumina plate to which copper layers are soldered on opposite sides. A chip is soldered to one of these layers and the other of these layers is soldered in turn to a metal heat sink. The chip is connected to respective copper strips which, in turn, are soldered to thermal strips originally forming part of a frame so that, after the device is encapsulated in a synthetic resin, the connecting members of the frame can be cut away to leave free ends of the latter strips exposed.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: March 18, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonio Perniciaro Spatrisano, Luciano Gandolfi, Carlo Minotti, Natale Di Cristina