Patents by Inventor Luigi Capodieci

Luigi Capodieci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150286763
    Abstract: Methods and apparatuses for pattern-based methodology for CAA and defect limited yield analysis are disclosed. Embodiments may include matching one or more patterns within a layer of an integrated circuit design layout to one or more pre-characterized patterns within a pattern library, determining respective critical areas of the one or more patterns based on respective pre-characterized critical areas of the one or more pre-characterized patterns, and predicting a defect limited yield of the layer based on the respective pre-characterized critical areas.
    Type: Application
    Filed: April 2, 2014
    Publication date: October 8, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Lynn WANG, Sriram MADHAVAN, Vito DAI, Luigi CAPODIECI
  • Patent number: 8924896
    Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: December 30, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Lynn Wang, Vito Dai, Luigi Capodieci
  • Patent number: 8918745
    Abstract: Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of density by comparing a first density of a first set of the features with a second density of a second set of the features; determining a region on the layer of a first feature to be resolved by the first mask; and inserting, within the region, a polygon to be resolved by the second mask based on the difference of density.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 23, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Lynn Wang, Sriram Madhavan, Luigi Capodieci
  • Patent number: 8910090
    Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lynn T. Wang, Vito Dai, Luigi Capodieci
  • Patent number: 8898606
    Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 25, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Rani Abou Ghaida, Ahmed Mohyeldin, Piyush Pathak, Swamy Muddu, Vito Dai, Luigi Capodieci
  • Publication number: 20140282301
    Abstract: Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of density by comparing a first density of a first set of the features with a second density of a second set of the features; determining a region on the layer of a first feature to be resolved by the first mask; and inserting, within the region, a polygon to be resolved by the second mask based on the difference of density.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Lynn WANG, Sriram Madhavan, Luigi CAPODIECI
  • Publication number: 20140245238
    Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Lynn T. Wang, Vito Dai, Luigi Capodieci
  • Publication number: 20140215415
    Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Lynn WANG, Vito Dai, Luigi Capodieci
  • Patent number: 8589844
    Abstract: Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: November 19, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Swamy Muddu, Abde Ali Kagalwalla, Luigi Capodieci
  • Patent number: 8555215
    Abstract: Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: October 8, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Yi Zou, Swamy Maddu, Lynn T. Wang, Vito Dai, Luigi Capodieci, Peng Xie
  • Publication number: 20130219347
    Abstract: Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
    Type: Application
    Filed: February 20, 2012
    Publication date: August 22, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yi Zou, Swamy Muddu, Lynn T. Wang, Vito Dai, Luigi Capodieci, Peng Xie
  • Patent number: 8516407
    Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: August 20, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Lynn T. Wang, Sriram Madhavan, Luigi Capodieci
  • Publication number: 20130212548
    Abstract: Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Swamy Muddu, Abde Ali Kagalwalla, Luigi Capodieci
  • Publication number: 20130198696
    Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.
    Type: Application
    Filed: January 30, 2012
    Publication date: August 1, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Lynn T. Wang, Sriram Madhavan, Luigi Capodieci
  • Patent number: 8418105
    Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 9, 2013
    Assignee: Globalfoundries, Inc.
    Inventors: Lynn T. Wang, Vito Dai, Luigi Capodieci
  • Patent number: 8124300
    Abstract: A method of correcting a lithographic mask is disclosed. The method can include detecting a location of the mask that corresponds to a wafer location having a structure that is printed with a larger than desired dimension and reducing a thickness of at least a portion of a mask feature corresponding to the wafer structure to locally increase transmissivity of the mask feature.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 28, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bhanwar Singh, Luigi Capodieci
  • Patent number: 8103979
    Abstract: An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: January 24, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yi Zou, Luigi Capodieci
  • Patent number: 7799517
    Abstract: A method of forming a feature on a device is disclosed. A photo resist layer is formed over the device and a dipole illuminator having a pole orientation axis in a first direction is used to expose a first geometrical pattern onto the resist layer. The first geometrical pattern is substantially oriented in the same direction as the pole orientation axis of the dipole illuminator. A dipole illuminator having a pole orientation axis substantially orthogonal to the first direction then is used to expose a second geometrical pattern onto the resist layer. The second geometrical pattern is oriented substantially orthogonal to the first direction.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: September 21, 2010
    Assignee: GlobalFoundries Inc.
    Inventor: Luigi Capodieci
  • Patent number: 7757190
    Abstract: Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 13, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vito Dai, Jie Yang, Norma Rodriguez, Luigi Capodieci
  • Publication number: 20100099032
    Abstract: An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate.
    Type: Application
    Filed: October 20, 2008
    Publication date: April 22, 2010
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Yi Zou, Luigi Capodieci